Re: [lwip-users] LwIP and memory section relocation

[Danish Ali]

Hi Mario,

Stm32f7 has a cache between normal RAM and the cpu. But no cache on DTCM.
This cache is not aware of any changes made to the RAM by DMA, and equally if 
you use DMA to read the RAM, it might read some if the RAM before the CPU has 
written everything to the RAM.

ST have some suggestions as to how to ensure cache-coherency before DMA from 
memory-to-peripheral and after DMA from peripheral-to-memory. I believe this 
will work but I wasn’t fully confident about the precise details.

What I do is different, in that I define a “buffers section” where I put all my 
DMA buffers including for LWIP (and UARTs, SDIO...), and disable the cache for 
that section.

Hope this helps,
Danish
> Dear All,
>    I am using LwIP with FreeRTOS on STM32F7 MCU and I am experimentig 
> an odd behaviour.
> 
> These MCU have two contiguous memory areas: a section close coupled to 
> the core (DTCM) and a normal RAM section.
> When I use the standard linker script the bss section and the LwIP 
> buffers ( "memp_memory_PBUF_POOL_base" (21K) ,"ram_heap" (9K) and other 
> buffers as memp_memory_PBUF_base 3K and some other with lower size) fall 
> into the DTCM memory and aberything is fine.
> 
> When I change the linker script and the bss section is allocated in the 
> normal RAM, the LwIP stack works badly, sometimes the device is not 
> reachable from network, sometimes (with other board e.g. Nucleo-F767ZI) 
> the ping loses more than half of the packets.