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Re: [lwip-users] Recv UDP Problem
From: |
Robin Iddon |
Subject: |
Re: [lwip-users] Recv UDP Problem |
Date: |
Fri, 25 Nov 2016 21:03:58 +0000 |
> Surely the cache memory gets invalidated automatically regardless of the
> source of writing to it?
No, often that is not the case; if the CPU(s) write to the memory (through the
cache) then the cache is valid when another thread or whatever reads back from
it; if a DMA peripheral (pretty much any other bus master - look at the bus
matrix in the docs) writes to RAM then it will bypass the cache.
You can in most CPUs have uncacheable memory regions such that you will always
get the data direct to/from RAM. In others you need to invalidate the cache
before reading the “volatile” memory. Depending on you performance
requirements there are trade offs between cache invalidation vs. reading
uncacheable memory region.
You’ll need to look at the M7 manual (not sure which one you’re using) to see
how the data cache coherency is managed.
The simplest solution is to map the memory reads/writes to descriptors and
packet buffers to go via the uncacheable memory space (often a case of ORing in
a high order address bit; not sure on M7).
- Re: [lwip-users] Recv UDP Problem, (continued)
- Re: [lwip-users] Recv UDP Problem, mgirke, 2016/11/21
- Re: [lwip-users] Recv UDP Problem, address@hidden, 2016/11/24
- Re: [lwip-users] Recv UDP Problem, mgirke, 2016/11/25
- Re: [lwip-users] Recv UDP Problem, Michael Steinberg, 2016/11/25
- Re: [lwip-users] Recv UDP Problem, Mike Fleetwood, 2016/11/25
- Re: [lwip-users] Recv UDP Problem, Michael Steinberg, 2016/11/25
- Re: [lwip-users] Recv UDP Problem,
Robin Iddon <=
- Re: [lwip-users] Recv UDP Problem, Robin Iddon, 2016/11/25
- Re: [lwip-users] Recv UDP Problem, Kenny Koller, 2016/11/26
- Re: [lwip-users] Recv UDP Problem, Michael Steinberg, 2016/11/26
- Re: [lwip-users] Recv UDP Problem, Kenny Koller, 2016/11/26
Re: [lwip-users] Recv UDP Problem, Sergio R. Caprile, 2016/11/21