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From: | Peter Barada |
Subject: | Re: [Ltib] patch to mtd-utils to dump ECC layout for a NAND MTD device |
Date: | Sat, 09 Jul 2011 10:34:45 -0400 |
User-agent: | Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.17) Gecko/20110424 Lightning/1.0b2 Thunderbird/3.1.10 |
On 07/08/2011 06:44 PM, Fritz Mueller wrote:
The problem I had was integrating support for a Micron NAND OMAP PoP device where the NAND has an internal 4-bit ECC engine that dictates the layout of the OOB/ECC bytes.Hey folks, > Peter Barada wrote:>> Adding in this code made life so much easier trying to hunt down and fix>> a but in YAFFS/NAND ECC compatibility between Linux and u-boot on my >> target....I've run up against a similar problem to the one Peter mentions that motivated this patch (in my case, JFFS2/NAND ECC compatibility issue between Linux and u-boot on a Freescale MPC8308 based target.) I've already taken a look at the NAND driver code being used by both u-boot and Linux, and at least by inspection both seem to be using the same ECC setup/strategy. I was wondering if Peter could comment here a little more on the nature of the problem he experienced and the eventual solution?
However the bootrom internal to the OMAP dictates teh first block use Hamming 1-bit ECCs so it can read the 2nd stage bootloader (x-loader) into SRAM. The kernel I was buillding ran on two differnt OMAP assemblies, one with the Micron NAND and the other used a Hynix (for industrial temperatures) that used a tradtiional 1-bit Hamming ECC.
Adding the code into the MTD utilities was a quick/easy way to prove at userspace that the ECC layout is indeed correct for each partition defined on each NAND part.
-- Peter Barada address@hidden
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