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[PATCH 9/9] mips: Optimize jit_htonr_us/jit_htonr_ui
From: |
Paul Cercueil |
Subject: |
[PATCH 9/9] mips: Optimize jit_htonr_us/jit_htonr_ui |
Date: |
Thu, 19 May 2022 10:39:18 +0100 |
Using the MIPS r2 instruction "WSBH", it is possible to perform 16-bit
and 32-bit endianness conversion in just a few opcodes.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
lib/jit_mips-cpu.c | 73 +++++++++++++++++++++++++++++-----------------
1 file changed, 47 insertions(+), 26 deletions(-)
diff --git a/lib/jit_mips-cpu.c b/lib/jit_mips-cpu.c
index 63e8c22..57b0c88 100644
--- a/lib/jit_mips-cpu.c
+++ b/lib/jit_mips-cpu.c
@@ -1770,13 +1770,19 @@ static void
_htonr_us(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
{
jit_int32_t t0;
- t0 = jit_get_reg(jit_class_gpr);
- rshi(rn(t0), r1, 8);
- andi(r0, r1, 0xff);
- andi(rn(t0), rn(t0), 0xff);
- lshi(r0, r0, 8);
- orr(r0, r0, rn(t0));
- jit_unget_reg(t0);
+
+ if (jit_mips2_p()) {
+ extr_us(r0, r1);
+ WSBH(r0, r0);
+ } else {
+ t0 = jit_get_reg(jit_class_gpr);
+ rshi(rn(t0), r1, 8);
+ andi(r0, r1, 0xff);
+ andi(rn(t0), rn(t0), 0xff);
+ lshi(r0, r0, 8);
+ orr(r0, r0, rn(t0));
+ jit_unget_reg(t0);
+ }
}
static void
@@ -1785,25 +1791,40 @@ _htonr_ui(jit_state_t *_jit, jit_int32_t r0,
jit_int32_t r1)
jit_int32_t t0;
jit_int32_t t1;
jit_int32_t t2;
- t0 = jit_get_reg(jit_class_gpr);
- t1 = jit_get_reg(jit_class_gpr);
- t2 = jit_get_reg(jit_class_gpr);
- rshi(rn(t0), r1, 24);
- rshi(rn(t1), r1, 16);
- rshi(rn(t2), r1, 8);
- andi(rn(t0), rn(t0), 0xff);
- andi(rn(t1), rn(t1), 0xff);
- andi(rn(t2), rn(t2), 0xff);
- andi(r0, r1, 0xff);
- lshi(r0, r0, 24);
- lshi(rn(t1), rn(t1), 8);
- orr(r0, r0, rn(t0));
- lshi(rn(t2), rn(t2), 16);
- orr(r0, r0, rn(t1));
- orr(r0, r0, rn(t2));
- jit_unget_reg(t2);
- jit_unget_reg(t1);
- jit_unget_reg(t0);
+
+ if (jit_mips2_p()) {
+ if (__WORDSIZE == 64) {
+ SLL(r0, r1, 0);
+ WSBH(r0, r0);
+ ROTR(r0, r0, 16);
+ extr(r0, r0, 0, 32);
+ } else {
+ WSBH(r0, r1);
+ ROTR(r0, r0, 16);
+ }
+ } else {
+ t0 = jit_get_reg(jit_class_gpr);
+ t1 = jit_get_reg(jit_class_gpr);
+ t2 = jit_get_reg(jit_class_gpr);
+
+ rshi(rn(t0), r1, 24);
+ rshi(rn(t1), r1, 16);
+ rshi(rn(t2), r1, 8);
+ andi(rn(t0), rn(t0), 0xff);
+ andi(rn(t1), rn(t1), 0xff);
+ andi(rn(t2), rn(t2), 0xff);
+ andi(r0, r1, 0xff);
+ lshi(r0, r0, 24);
+ lshi(rn(t1), rn(t1), 8);
+ orr(r0, r0, rn(t0));
+ lshi(rn(t2), rn(t2), 16);
+ orr(r0, r0, rn(t1));
+ orr(r0, r0, rn(t2));
+
+ jit_unget_reg(t2);
+ jit_unget_reg(t1);
+ jit_unget_reg(t0);
+ }
}
static void
--
2.35.1
- [PATCH 0/9] MIPS improvements, Paul Cercueil, 2022/05/19
- [PATCH 1/9] mips: Properly define jit_mips2_p(), Paul Cercueil, 2022/05/19
- [PATCH 2/9] mips: Fix is_low_mask() to support -1, Paul Cercueil, 2022/05/19
- [PATCH 3/9] mips: Optimize jit_andi further, Paul Cercueil, 2022/05/19
- [PATCH 4/9] mips: Optimize jit_bmsi / jit_bmci, Paul Cercueil, 2022/05/19
- [PATCH 5/9] mips: Optimize jit_extr_ui, Paul Cercueil, 2022/05/19
- [PATCH 6/9] mips: Use 32-bit MUL opcode for mulr() on 32-bit MIPS, Paul Cercueil, 2022/05/19
- [PATCH 7/9] mips: Optimize jit_lei / jit_lei_u, Paul Cercueil, 2022/05/19
- [PATCH 8/9] mips: Optimize jit_gei/jit_gei_u, Paul Cercueil, 2022/05/19
- [PATCH 9/9] mips: Optimize jit_htonr_us/jit_htonr_ui,
Paul Cercueil <=