Re: plotting transfer function in octave 5.2: How to fix error: set: "dataaspectratio' must be finite

[shall689]

> Do mean reducing innerloop (G1, H1, F1) to one block?
Yes (also includes ZOH1).  There would be two variables in that equation, P
and I.  I would adjust P and I so that the equation is in the stable region
and has a good step response.

> G1 and G2 actually are digital controllers, right? Therefore, they
> already are discrete-time. If there is a ZOH after G1 (the DAC at the
> boundary from discrete- to continuous-time), the continuous-time system
> (H1, H2, F1, F2) has to be discretized using the ZOH-method.
Yes, G1 and G2 will be implemented on an FPGA.
I thought it would be easier to work with the equation in the s domain. 
Also, from what I have seen (PSIM
(https://www.youtube.com/watch?v=rNMlaq8xABE) and
https://www.youtube.com/watch?v=yetLPW9sQaI&list=PLUMWjy5jgHK0MLv6Ksf-NHi7Ur8NRNU4Z&index=3),
you can do the analysis/simulation in the s domain and then convert to the z
domain.

> If you design G1 and G2 in the Laplace-domain, I think it would not be
> correct to use the ZOH-method for getting the algorithm you have to use
> for the controllers, since the input of the controllers is not constant
> during two samples.
Doesn't ZOH1(s) account for the hold/delay in the Laplace-domain?  

Are saying that I should do the following (e.g. inner loop):
Discretize G1(s)*H1(s)/(1+G(s)*H1(s)) using ZOH method and then perform the
analysis on the stability and step response?  One issue is that the s domain
has two variables (i.e. P and I) and that would make the conversion from the
s domain to z domain a little more cumbersome.

What steps would you take to come up with good P and I gains for both the
inner and outer loop?

>>Why is there a second ZOH? Do you have two control inputs into the
>>continuous-time system?

After thinking about it, there probably only needs to be one ZOH in the
model.  In the digital domain it will be inherent in the z domain equations
because the z domain equations will be converted from the s domain using the
ZOH method.

The FPGA will get all the feedback from a simultaneous sampling multichannel
ADC.  Therefore all the feedbacks will be read a the same time.  Three
feedbacks are used: inverter current and inductor current (both for the
inner loop and can be thought of as capacitor current) and output voltage
for the outer loop.  
Both controllers (inner and outer) operate in parallel.  The outer loop uses
the voltage reference and the current  output voltage feedback sample.  The
inner loop uses the previous output of the inner loop and the current
inverter and inductor current feedbacks.

Stephen

 



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