Re: Dependencies for clean rule

[David Boyce]

A few notes:

1. You can often make use of MAKECMDGOALS to treat clean targets specially.
The manual gives an example.

2. I've evolved the pattern below for clean targets:

.PHONY: clean
clean: cleanups := $(wildcard *.o *.d core)
clean:
        $(if $(cleanups),$(RM) -r $(cleanups))

Of course the list "*.o *.d core" is just for illustration purposes. What I
like about this pattern is that when it has files to remove it shows you
what they were and if the state is already clean rather than running a
useless "rm -f *.o *.d core" it says, correctly, "Nothing to be done for
'clean'."

3. I've written makefiles in the past that make use of user-defined macros,
eval, whatever to maintain a variable (say "targets") which is a list of
all defined targets. With that you could plug $(targets) in as the list in
the above example. It may be a bit of overkill but it is doable.

On Mon, Jul 15, 2019 at 12:56 PM Erik Rull <address@hidden> wrote:

> Hi all,
>
> I have several targets that depend on each other.
> For cleaning them up, I have to take care that the clean dependencies are
> just
> the other way round.
>
> e.g.
>
> a: b c
> b: d e
> c:
> d:
> e:
>
> If I want to make a the dependencies assert that the build order is
> correct.
> If I want to make "clean" e.g. c, I should clean a first.
>
> Is there a way to find the "reverse-order" of the dependencies? Of course,
> I
> could manually write the clean-rule-dependencies, but that would be too
> easy
> (and generate additional errors when the number of targets and
> dependencies are
> bigger).
>
> Maybe someone solved that already, I did not yet find a smooth solution
> for that.
>
> Thanks in advance.
>
> Best regards,
>
> Erik
>
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