Calling functions to define make rules.

[Brian Cowan]

All, 

I'm dealing with some odd behavior differences between make tools that are 
supposed to be compatible with GNU make and need to know if this is a 
valid construct in a makefile:

----------------------------------------------
filelist1 = a b c d e f g h i j k l
filelist2 = aa bb cc dd ee ff gg hh ii jj kk ll
filelist3 = aaa bbb ccc ddd eee fff ggg hhh iii jjj kkk lll

define hope
$(1):
        echo $(0) $(1) make file call command

endef

hope1 = $(foreach x,$(value $(1)),$(call hope,$(x)))

$(foreach z,filelist1 filelist2 filelist3, $(info $(z)))

$(foreach z,filelist1 filelist2 filelist3, $(call hope1,$(z)))

all: $(filelist1) $(filelist2) $(filelist3)
----------------------------------------------

When I call it using clearmake's GNU make emulation . I get make output 
that shows that it is "building" all 36 "targets."

When I use GNU make 3.73, 3.78.1, or 4.2.1 (the latter under Cygwin) I get 
this:
address@hidden /cygdrive/c/Users/Brian
$ make -f makefile.call.txt all
filelist1
filelist2
filelist3
makefile.call.txt:15: *** multiple target patterns.  Stop.

So, my question is: What, if anything, am I doing wrong here? Yes, this is 
an INCREDIBLY stilted example. The actual makefile setup is horrifyingly 
complex, and this is the first part I'm trying to wrap my skull around.

=============================================================
Brian Cowan
ClearCase/Licensing Software Advisory Team (SWAT)
HCL Technologies at IBM
IBM Cloud Support
550 King St
Littleton MA 01460

Phone: +1 978 899 5436