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Re: Issue with foreach statement
From: |
Brian Vandenberg |
Subject: |
Re: Issue with foreach statement |
Date: |
Wed, 27 Jul 2016 11:26:45 -0600 |
​Fortunately this is rather easy to reproduce without foreach:
> $ cat /tmp/makefile
>
> define TEST_MACRO =
> $(eval a=b)
> $(eval a=b)
> endef
>
> $(call TEST_MACRO)
>
> $ make -f /tmp/makefile
> /tmp/makefile:8: *** missing separator. Stop.
The issue is that the evaluation of TEST_MACRO produced a non-empty string
consisting of whitespace. Once make begins evaluating a line as in my
example it assumes you're going to do something on that line, but what it
gets back is something it cannot interpret as a valid makefile directive.
You can resolve this problem by wrapping the foreach in a $(strip):
> $(strip $(foreach ...))
-brian