Re: How must I use override and export with sub makefiles

[Oleksandr Gavenko]

On 2012-10-30, José Luis García Pallero wrote:

> Hello:
>
> I have three makefiles:
> [SKIP]
>
I write just two:

Makefile:
================================================================
ifeq 'xlc' '$(CC)'
  override CC := xlc_r
endif
export CC

all: export CC := $(CC)
all:
        @echo $(CC)
        make -f Makefile.sub
        make -f Makefile.sub CC=$(CC)

Makefile.sub
================================================================
all:
        @echo CC - $(CC)

When run:

  $ make CC=xlc

  make CC=xlc
  xlc_r
  make -f Makefile.sub
  make[1]: Entering directory `/home/user/devel/tmp/1'
  CC - xlc
  make[1]: Leaving directory `/home/user/devel/tmp/1'
  make -f Makefile.sub CC=xlc_r
  make[1]: Entering directory `/home/user/devel/tmp/1'
  CC - xlc_r
  make[1]: Leaving directory `/home/user/devel/tmp/1'

So in second case I get what you want, but not as you want ))

> As you can see, Makefile.par changes the CC variable using override if in
> the command line is passed the value 'xlc' and then exports it. The actual
> compilation is done by Makefile.sub. My problem is that when the CC variable
> is changed and exported in Makefile.par, the modified result is viewed in
> Makefile, but not in Makefile.sub, that uses de CC value passed in the
> command line. How can I use override and export in order to use the modified
> CC variable in Makefile.sub
>
Quotation from manual:

  The `override' directive was not invented for escalation in the war between
  makefiles and command arguments. It was invented so you can alter and add to
  values that the user specifies with command arguments.

Just write common configure part (I introduce new kind - TOOLSET - a set of
compelers and linkers etc, we personally use msvc_6, msvc_7, cl_10, gcc, xlc,
etc as values):

  ifeq '' '$(TOOLSET)'
    TOOLSET := gcc
  endif
  export TOOLSET

  # Default (and for TOOLSET=gcc).
  CC := gcc

  ifeq 'xlc' '$(TOOLSET)'
    CC := xlc
    ifeq 'linux' '$(host_os)'
      CC=xlc_r
    endif
  endif

and include it on each Makefile.*:

Makefile
================================================================
include Makefile.common
all:
        @echo CC - $(CC)
        $(MAKE) -f Makefile.sub

Makefile.sub
================================================================
include Makefile.common
target:
        echo $(CC)


  $ make TOOLSET=gcc

  CC - gcc
  make -f Makefile.sub
  make[1]: Entering directory `/home/user/devel/my-devel/exp/make/suit'
  sub.CC - gcc
  make[1]: Leaving directory `/home/user/devel/my-devel/exp/make/suit'

  $ make TOOLSET=xlc

  CC - xlc
  make -f Makefile.sub
  make[1]: Entering directory `/home/user/devel/my-devel/exp/make/suit'
  sub.CC - xlc
  make[1]: Leaving directory `/home/user/devel/my-devel/exp/make/suit'

  $ make TOOLSET=xlc host_os=linux

  CC - xlc_r
  make -f Makefile.sub
  make[1]: Entering directory `/home/user/devel/my-devel/exp/make/suit'
  sub.CC - xlc_r
  make[1]: Leaving directory `/home/user/devel/my-devel/exp/make/suit'

################################################################

Notes:

 * don't call 'make', call '$(MAKE)' instead
 * don't use tab as first char in variable assignment, like do so in:

    ifeq ($(CC),xlc)
        override CC=xlc_r
    endif

before override (all that start with TAB is command for target, and never
become variable assignment)!!

Hope I help you.

################################################################

But question about 'export' and 'override' on same variable is open when it
come from makefile argument...

-- 
Best regards!