Re: Skipped secondary expansions inside make rules

[Dmitry N. Mikushin]

> Why did you use $$?

Well, I think because my understanding of $$ is poor. From manual I
understood $$ should be issued in cases when we want to evaluate a
variable whose name is constructed from other tokens. Why it is not
the case here? Indeed, using single $ makes it to work properly, thank
you, Philip!

- D.

2011/3/4 Philip Guenther <address@hidden>:
> On Fri, Mar 4, 2011 at 7:44 AM, Dmitry N. Mikushin <address@hidden> wrote:
> ...
>> %.so: DEPLIBS = $$($(LIBNAME)_DEPLIBS)
>> %.so: dirs
>>       address@hidden Linking shared library $(LIBNAME) ...
>>        $(CPPCOMP) $(CPARAMS) -Wl,--no-undefined -shared -o $@ -L$(OUTDIR) \
>>                -Wl,--gc-sections -Wl,--whole-archive -Wl,-static \
>>                $(addprefix -l, $(STATIC_LIBS)) \
>>                -Wl,--no-whole-archive -Wl,-call_shared $(DEPLIBS)
>>
>> If it is applied to bin/libfoo.so, LIBNAME becomes FOO, DEPLIBS
>> becomes FOO_DEPLIBS, and final command works incorrectly because $$
>> expansions were not actually performed. Why are expansions skipped and
>> what can I do to get them working in this case?
>
> The expansion is skipped because you used $$.  Why did you use $$?
>
>
> Philip Guenther
>