using variables in makefile

[mahmoodn]

In my makefile I have these lines:
GPGPUSIM_ROOT := $(GPGPUSIM_ROOT)
include $(NVIDIA_CUDA_SDK_LOCATION)/C/common/common.mk

I have set two variables in bash.rc file. The results for echo are:
address@hidden:~$ echo $GPGPUSIM_ROOT
/home/mahmood/gpgpusim/gpgpu-sim_v2.1.1b

address@hidden:~$ echo $NVIDIA_CUDA_SDK_LOCATION
/home/mahmood/NVIDIA_GPU_Computing_SDK

Now when I run the makefile I get this error:
Makefile:<line number>: /C/common/common.mk: No such file or directory
make: *** No rule to make target `/C/common/common.mk'.  Stop.

I have searched to find why environment variables don't work in makefile,
but didn't find anything useful. I am not expert in makefile structures but
I have compiled makefiles that contain
-I$(VARIABLE)/include and they are successful. So what is the difference
here? 
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