Re: Implicit rule results in header file compilation attempt

[Paul Smith]

On Wed, 2008-02-13 at 13:12 +0000, Rob Desbois wrote:
> I have a makefile including the following prerequisites rule:
>    foo: bar.h
> where foo.cpp exists in current directory
> 
> The additional prerequisite 'bar.h' is being passed as an input file
> to $(CXX) by the make's implicit rule:
>    $(LINK.cpp) $^ $(LOADLIBES) $(LDLIBS) -o $@
> (obtained from make -p)
> 
> The additional prerequisites are essentially for determining when foo
> must be rebuilt, but the rule seems peculiar in not stripping out
> header files.  Is there any particular reason?

Well, because having an executable depend on a .h file is not something
people normally do.  Object files depend on .h files, because object
files have to be rebuilt when the .h changes.  Executables depend on
object files, because the executable is relinked when the object file
changes.

If you're going to add .h files to the prerequisites list, why not add
the .c files as well?  And the source code control master files?  And
the yacc/lex files?  Etc.  You can't write a rule to exclude any type of
unwanted file that might appear in the prerequisites list.

You could TRY to write a rule to _include_ only the types of files that
you wanted, but there are many different types here as well
(.o, .a, .so, etc.) so it's not that straightforward either.

When writing default rules, we gear them towards the common case.

> And is the best way to avoid this to provide my own implicit rule
> instead which filters out words matching %.h from $^ ?

Yes, if you really need to have the executable depend on the .h, then
you'll need to write your own rule.

-- 
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