Re: Expanding a variable in the dependencies

[Kristof Provost]

On 2007-07-19 10:05:58 (+0300), Or Goshen <address@hidden> wrote:
> 
> 
> On 7/19/07, Kristof Provost <address@hidden> wrote:
> 
>     On 2007-07-18 22:41:26 (+0300), Or Goshen <address@hidden> wrote:
>     > Hi
>     >
>     > I have the following make file:
>     >
>     > TEST_LO=test.lo
>     >
>     > %.so: $($*_LO)
>     >         $(CC) $(LDFLAGS) -shared -Wl,-soname,$*.so.0 -o $*.so $($*_LO)
>     >
>     > %.lo: %.c
>     >         $(CC) $(CFLAGS) -fPIC -o $*.lo -c $*.c
>     >
>     >
>     > When I execute "make TEST.so" I get:
>     >
>     > $ make TEST.so
>     > gcc -shared -Wl,-soname,TEST.so.0 -o TEST.so test.lo
>     > gcc: test.lo: No such file or directory
>     > make: *** [TEST.so
>     > ] Error 1
>     >
>     > My question is - why doesnt it expand "$($*_LO)" in the dependencies as
>     well ?
>     > (I got the file "test.c" in the directory)
> 
>     Make will determine prerequisites based on the variable value when the
>     line is parsed, not when the target is built. That means make isn't
>     aware that test.lo is a prerequisite. Try putting '@echo prereqs: $^'
>     before the compile statement in the %.so rule.
> 
>     Fortunately GNU Make has .SECONDEXPANSION.
>     Read the manual, specifically this bit:
>     http://www.gnu.org/software/make/manual/make.html#Secondary-Expansion
> 
>     You can rewrite your makefile to become:
> 
>     .SECONDEXPANSION:
> 
>     TEST_LO=test.lo
> 
>     %.so: $$($$*_LO)
>         $(CC) $(LDFLAGS) -shared -Wl,-soname,address@hidden -o $@ $^
> 
> 
> When I try to use second expansion as you suggested "make -d  TEST.so" returns
> :
> 
>   .
>   .
>   .
>   Considering target file `TEST.so'.
>    File `TEST.so' does not exist.
>    Looking for an implicit rule for `TEST.so'.
>    Trying pattern rule with stem `TEST'.
>    Trying rule prerequisite `$($*_LO)'.
>    Trying pattern rule with stem `TEST.so'.
>    Trying implicit prerequisite `TEST.so,v'.
>    Trying pattern rule with stem `TEST.so'.
>    Trying implicit prerequisite `RCS/TEST.so,v'.
>    Trying pattern rule with stem `TEST.so'.
>    Trying implicit prerequisite `RCS/TEST.so'.
>    Trying pattern rule with stem `TEST.so'.
>    Trying implicit prerequisite `s.TEST.so'.
>    Trying pattern rule with stem `TEST.so'.
>    Trying implicit prerequisite `SCCS/s.TEST.so'.
>    Trying pattern rule with stem `TEST'.
>    Trying rule prerequisite `$($*_LO)'.
>    Looking for a rule with intermediate file `$($*_LO)'.
>     Avoiding implicit rule recursion.
>     Trying pattern rule with stem `$($*_LO)'.
>     Trying implicit prerequisite `$($*_LO),v'.
>     Trying pattern rule with stem `$($*_LO)'.
>     Trying implicit prerequisite `RCS/$($*_LO),v'.
>     Trying pattern rule with stem `$($*_LO)'.
>     Trying implicit prerequisite `RCS/$($*_LO)'.
>     Trying pattern rule with stem `$($*_LO)'.
>     Trying implicit prerequisite `s.$($*_LO)'.
>     Trying pattern rule with stem `$($*_LO)'.
>     Trying implicit prerequisite `SCCS/s.$($*_LO)'.
>    No implicit rule found for `TEST.so'.
>    Finished prerequisites of target file `TEST.so'.
>   Must remake target `TEST.so'.
> make: *** No rule to make target `TEST.so', needed by `all'.  Stop.
> 
> 
>     %.lo: %.c
>         $(CC) $(CFLAGS) -fPIC -o $@ -c $<
> 
> 
>     Kristof
> 
> 
> 
> What am I doing wrong ?

What make version are you using? I believe SECONODEXPANSION has been
supported since GNU Make 3.80 or 3.81.

There's one more problem, but I don't think it's causing this issue.
You're trying to build test.so, so make will expand $($*_LO).
$* matches the % part of %.so, in this case test, so make will expand
$(test_LO), which is different from $(TEST_LO).
The first is an empty variable, so there are no prerequisites for
test.so, and you still see the original problem.

Regards,
Kristof