Re: how to methodically generate a set of rules?

[Robert P. J. Day]

On Tue, 28 Mar 2006, Nick Patavalis wrote:

> On Tue, Mar 28, 2006 at 03:32:20AM +0300, Nick Patavalis wrote:
> >
> > Don't use "make" to do the loop. Use the shell for this. Use the shell
> > to generate a "new" Makefile, and included it from you "main"
> > Makefile. Something like this:
> >
> >   auto.mk : s1.c s2.c ... sN.c
> >       rm -f $@
> >       for i in $+; do
> >           write_rule $i >> $@
> >       done
> >
> >   include auto.mk
> >
>
> Correcting myself. This has the disadvantage of re-calculating *all*
> rules if *one* source-file chagnes. You could do better (recalculate
> only the relevant rules) like this: ::
>
>   SRCS := s1.c s2.c ... sN.c
>
>   %.mk : %.c
>       write_rule $< >> $@
>
>   include $(SRCS:.c=.mk)
>
> This will of-course create many "autogenerted" makefiles, one for
> every source-file, which will all get included.

  i'd actually thought of that but here's the problem -- i'm trying to
add this feature into an existing makefile which supports getting its
source files from one remote location and building the resulting
object files in a *second* location, while possibly running from a
*third* location.  because of that, i'm trying very hard *not* to have
to create temporary makefiles so i'd like to do *everything* using
pattern rules.  let me give one more explanation of what i'm trying to
do with a little more detail to see if i've overlooked anything.

again, i have a given list of C source files, each of which has the
following structure:

        blah.c:

        #ifdef OBJ_fred
        ... what will be compiled to generate fred.o ...
        #endif

        #ifdef OBJ_astro
        ... what will be compiled to generate astro.o
        #endif

        ... and so on ...

  there is no clear pattern between the name of the source file and
the names of the object files that it can generate.  each source file
will be compiled several times, defining a different preprocessor
directive each time to generate the corresponding object file.  so
far, so good?

  for a file like the one above, the generated makefile rule would
resemble:

fred.o astro.o:  blah.c
        ... funky rule to build each object file ...

  now, given the list of source files, for each source file, i could
easily generate the list of corresponding object files using "grep"
so, for a given ${SRCFILE}, i would have:

  OBJFILES := $(addsuffix .o,
                $(shell grep -h "^\#ifdef OBJ_" ${SRCFILE} | \
                sed -e "s/^\#ifdef OBJ_//"))

in other words, given a source file, it's pretty easy to reach into it
and create the list of object files.  so if i had a loop, i could just
loop over all of the source files, one at a time, and do the above.

  without a "loop" construct to do this, i believe i know how to do
this in one fell swoop but it would get sort of ugly.  what i figured
was that i could have a single rule that had, as targets, *all* object
files that would be generated by all of the source files, and the
dependencies and commands in that rule would then, for each of those
object files, generate its source file name, etc. etc.  yuck.  doable,
but yuck.

  unless someone has a better idea.

rday