Re: how does Make process command sections before passing to the shell

[Greg Chicares]

On 2006-3-8 16:36 UTC, Andrew Ferguson wrote:
>
> [...] I am trying
> to understand which characters have special significance in a rule
> command section and which participants are involved in processing them.

Dollar sign is special: it marks 'make' variables and functions
that get expanded in rules.

.PHONY: all
all:
        @echo xyzzy has the value $(xyzzy)
        This is a literal dollar sign: $$

$make xyzzy='Some string.'
xyzzy has the value Some string.
This is a literal dollar sign: $

Characters in "@+-" at the beginning of a command have special
meanings, too; 'make' comments begin with '#'; and, of course,
a command needs to begin with a tab character.

> For example, given
>
>     target: dep1.ext dep2.ext dep3.ext
>         command --opt1 val1 etc..
>
> how can you predicate which characters will be given special
> significance? It seems the section of text after the rule header is
> processed by make itself before being passed to the underlying shell?

Yes, although make finds nothing to substitute in the literal
string given above.

> At the moment, I'm aware that the following may do some textual
> processing before passing the commands on to the next layer
>     (1) Make

As long as you don't prefix a command with '@', you'll see
what 'make' actually passes to the shell.

>     (2) A shell (or can tools sometimes be invoked direct by OS process
> creation api?)

The manual says: "When it is time to execute commands to update
a target, they are executed by making a new subshell for each
line. (In practice, make may take shortcuts that do not affect
the results.)" Ignoring a blank line is one such shortcut.

>     (3) The tool itself

The tool receives whatever the shell gives it. You could think
of that as involving further processing. For instance, in DOS,
programs typically expand wildcards in arguments, because
COMMAND.COM doesn't.