Re: Need to get $MAKEFLAGS value only

[Soren A]

Greg, regarding the following, you might be interested (it is
tangential) in the article I posted back in Sept (follows). 

gk <address@hidden> wrote around 17 Oct 2002
news:address@hidden: 

> I would like to call make and get the value of $MAKEFLAGS without
> actually building anything.
> 
> In other words, rather than emulating Gnu make's options parsing, I
> would like to call Gnu make, passing some parameters and get back the
> value of $MAKEFLAGS, without the -C, -o, -W, -f options which aren't
> ever included in $MAKEFLAGS, and without the targets of course.
> 
> Of course I could call my application back, from a makefile rule, and
> get $MAKEFLAGS since it is always exported but then I'd be in a
> subshell which is not what I want.
> 
> I don't suppose there is a way to do this since there is no option 
> documented. I was just wondering if there are library functions I
> could call to do this.

Soren A <address@hidden> wrote
around 12 Sep 2002 news:address@hidden:

 -------------------------------------------------------------------------
|  From: Soren A <address@hidden> |
|  Newsgroups: gmane.comp.gnu.make.general                                |
|  Subject: A behavior I wonder about                                     |
|  Date: Thu, 12 Sep 2002 06:17:06 +0000 (UTC)                            |
|  Message-ID: <address@hidden>                |
 -------------------------------------------------------------------------

> Hello,
>
> Using GNU 'make' in various unusual ways, I have discovered a thing
> that seemed a bit odd to me at first.
>
> If I want to access, from inside a Makefile, the directories which are
> going to be searched for included makefiles (via the 'include'
> directive), I may look at the built-in macro MAKEFLAGS or MFLAGS. Is
> there any other possibility that I missed in the documentation? It
> would be cool if there was a macro like "MAKEDIRS" that could be
> checked.
>
> Assuming that what I know is all there is to know about accessing the
> 'include' dirs, then ... what I might get for MAKEFLAGS is something
> that looks like this:
>
> --warn-undefined-variables -wI /cdv/g/src/common-vmk
>
> and what I have in my environment is put there by a statement that
> looks like this:
>
> export MAKEFLAGS="--unix --warn-undefined-variables --print-directory
> \ --include-dir=/cdv/g/src/common-vmk"
>
> There's an anomaly in that 'make' seems to drop the
> '--print-directory' flag entirely. Maybe that's documented so let's
> skip that for the moment.
>
> What 'make' seems to do is to create a string that embodies the most
> compressed, brief possible form the options statement could take. What
> is mostly of interest to me is that the single-letter options 'w' (and
> if '-k' is given as an argument, it too) are bunched together with the
> first -I statement. In order to get access to which directories are
> being searched for Makefiles (and I do acknowledge that this is an
> unusual thing to want to do and probably hasn't come up much), the
> intervening option letters between '-' and 'I' must be removed. This
> requires quite a little bit of manipulation to accomplish:
>
> DEFNUL =
> s = $(DEFNUL) # what we want is the SPACE between
> # the null macro and the hash.
> DECRUFTED = $(filter-out - -- --%,$(MFLAGS))
> LOOK4WHERE= $(subst -I$s,,$(patsubst -%I,-I,$(DECRUFTED)))
>
> (BTW, then, once we have a list of include dirs to search, we can do
> something like this:
>
> FOUND_CPUTOOL = $(firstword \
> $(wildcard $(addsuffix /get_hostcpu.mk,$(LOOK4WHERE) \
> /usr/local/include)))
>
> and can do something with that file we've found, if we find it.)

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