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Re: Verilog syntax (Was: parameter usage in simulation)
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From: |
Felix Salfelder |
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Subject: |
Re: Verilog syntax (Was: parameter usage in simulation) |
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Date: |
Mon, 20 Apr 2020 12:47:57 +0200 |
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User-agent: |
NeoMutt/20170113 (1.7.2) |
On Mon, Apr 20, 2020 at 12:29:34PM +0200, patrick wrote:
> But trying to run a simple sweep on the Resistor gives:
>
> .verilog
I suspect that you are running gnucap with the -b flag. this switches on
spice mode, and in spice mode, the first line is the title (effectively
ignored).
try to drop the -b, and put "verilog", without the dot, into the first
line.
cheers
felix