Make with multiple variables for multiple targets.

[Bill Godfrey]

Hello. I first raised this question on comp.programming. I was advised that
this group may be better placed. This article contains much of both posts
with some editing. If I may ask your collective assistance please?

We have a single makefile which is called...
make BUILD=foo
(Other BUILD values are 'bar' and 'baz', as tradition dictates.)

Inside the makefile, we have...

CFLAGS=$(CFLAGS_$(BUILD)) $(ADDED_CFLAGS)
LFLAGS=$(LFLAGS_$(BUILD)) $(ADDED_LFLAGS)
CFLAGS_foo=gcc compiler options specific to the foo build
LFLAGS_foo=linker options specific to the foo build
CFLAGS_bar=gcc compiler options specific to the bar build
LFLAGS_bar=you get
CFLAGS_baz=the general
LFLAGS_baz=idea

The BUILD variable also finds it's way into the general .c -> .o rule.

build/$(BUILD)/%.o: %.c
    $(CC) $(CFLAGS) $< -o $@

So far, so good. But, here's the problem.

We can't get a true 'make all'. At the moment, the commands for 'all' are
recursive make calls with the required BUILD value. This is a most
displeasing situation. I'd rather just say...
all: build/foo/foo.hex build/bar/bar.hex build/baz/baz.hex

I'd like to be able to give the command 'make build/foo/blip.o' rather
than 'make BUILD=foo build/foo/blip.o'.

The 'bar' build would like to borrow a .o file from the 'foo' world. It
would be great if we just put the file in the list of prerequisties and
have make sort it out. (I'm using a recurrsive make call to dela with it.)


All in all, I'm trying to avoid the pitfalls identified in 'Recursive make
considered harmful', but finding recursive make unavoidable.

Ideally, I'd something like this, which I'd like to illustrate with some
invented syntax...

build/MAKEVAR(BUILDTYPE)/%.o: %.c
    $(CC) $(CFLAGS_$(BUILDTYPE)) -c $< -o $@

MAKEVAR() is my invented make syntax. It can match any string inside a
target, much like % can. When the commands to create the target from the
dependents is run, that part of the string becomes a new variable for those
commands, using the name in brackets.

So, using the above make code with (say) build/foo/mysrc.o as a target,
with mysrc.c as an up-to-date dependent, the following steps would take
place...

Target matches template.
Template includes MAKEVAR().
Name from MAKEVAR is extracted. 'BUILDTYPE'.
Value from target is extracted. 'foo'.
Variable BUILDTYPE is created (or overwritten) with value 'foo'.
Commands are executed...
   $(CC) is subsituted with (say) 'gcc'.
   $(BUILDTYPE) is substituted with 'foo'.
   $(CFLAGS_foo) is substituted with (say) '-DBUILD=FOO -mfoo'.
   Full command is 'gcc -DBUILD=FOO -mfoo -c mysrc.c -o build/foo/mysrc.o'.

That's my ideal. If someone could please tell me "make has no facility like
that!", I'll consider alternatives.

Many thanks.

Bill, making bacon.