Re: Higher resolution timers

[Colin D Bennett]

On Fri, 23 May 2008 13:55:21 +0200
Marco Gerards <address@hidden> wrote:

> Colin D Bennett <address@hidden> writes:
> 
> > On Mon, 12 May 2008 09:33:54 -0700
> > Colin D Bennett <address@hidden> wrote:
> >
> >> I think that using the TSC (w/ RDTSC instruction) and calibrating
> >> it with a quick 2-3 RTC tick loop at startup might be the easiest
> >> option.
> >
> > Just wondered if something like this would be a practical way to go:
> 
> Well, I only had a quick look and this might be a good way to measure
> the clock speed.  BTW, can you please make sure you use our coding
> style?  Are the 2-3 loops based on some calculations or only a guess?

Of course I will adhere to the GRUB coding style.  The snippet I posted
was just basically just quick pseudocode (not actually compiled) based
on 10 minutes of thought.  I did not take time to format the code style
but surely I would before submitting an actual patch.

I think we only need 1 full RTC timer tick (i.e. 1/18 of a
second) to figure out how many TSC cycles correspond to one second of
real time.  The code has to first synchronize to the starting edge of
an RTC tick, so that is the loop:
   do { ... } while (start_tick == initial_tick);
Then the number of elapsed TSC cycles until the next RTC tick is
calculated and the TSC cycles per second is calculated.

(As I said, this is untested and incomplete scratch work as a starting
point for a discussion, and it might not even compile.)


> There might be a problem with using this instruction.  Are clock
> cycles actually measured after using the "halt" instruction?  If not,
> the use of such instruction might not generally used in GRUB :-/

Thanks for thinking of that. According to
<http://www.scl.ameslab.gov/Projects/Rabbit/menu4.html>, the TSC
continues counting even when the CPU executes the HLT instruction:

   The TSC is set to 0 at system reset. It presently increments once per
   processor cycle, and is 64 bits wide. Only CPL = 0 can modify TSC,
   and then only the lower 32 bits can be set, while the upper 32 bits
   are cleared. We do not recommend changing TSC, and the library does
   not permit it. The TSC will continue to increment in the halt state
   (HLT instruction).

Therefore, I think that that the HLT instruction in GRUB will not
negatively impact the use of RDTSC.

Regards,
Colin

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