Re: sym to verilog-ams

[al davis]

On Tue,  5 Apr 2022 12:24:11 +0200 (CEST)
karl@aspodata.se wrote:
> A, "diff orig_file round_trip_file | wc -c" == 0
> B, sort files by some program and there will be no diffs
> C, converting files to jpg's and they they don't show any differences
> D, the netlists produced with alt. orig/round_trip produces no diff
> E, something else
> 
> For choise A, one could just include the whole orig_file in the verilog
> file as a comment or something.
> 
> For B, I have a sorting program at:
>  http://aspodata.se/git/openhw/bin/sort_sch.pl and GedaSch.pm
> yes, it needs testing.
> 
> For C, there is lepton-schdiff/schdiff.
> 
> About D, the unnamed nets might have different numberings.


To determine the answer, remember how the files are used.

It's all about the circuit.  The drawing is just a way to present the
circuit

A makes it tempting to cheat.

Something like D, the same circuit, is really the obvious answer, but I
would cut some slack on some things that are artifacts of the moment,
such as the order in the list or the numbering of unnamed nets.

How the files are used ...  Why do we care about the round trip?

One reason is to validate the conversion.  If the immediate goal is to
transform it in one direction, transforming it back is one way to
validate the correctness of the transformation.   The lossless round
trip is a noble goal, but in practice it may be very difficult to do
strictly, but almost may be good enough.  In this sense, it is
important to actually transform both ways, and not get the match by
stashing the original text.

Another way the files are used is that there may be some changes as it
travels.  One possibility is that you draw a schematic, simulate it,
and the simulator augments it with some data to back-annotate.  So you
hit "refresh" in the schematic, and it updates the parts that changed,
leaving the rest the same.

Another is the transfer from one to another similar applications.  On
the schematic side, there is Lepton, Qucs, Kicad, Xcircuit, .....   One
goal of this is to get these to play together nicely.  There's also
layout.  (pcb, kicad)  

There's commercial apps too.  

Regarding the netlists produced .........  Once you have the Verilog
version, it makes sense to use it as an intermediate to get to any
other netlist.