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Re: sym to verilog-ams
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From: |
karl |
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Subject: |
Re: sym to verilog-ams |
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Date: |
Tue, 5 Apr 2022 12:24:11 +0200 (CEST) |
Felix:
...
> The goal is to reproduce the sym file back from its verilog
> representation (round-trip).
...
So, what is really the goal (for both sym and sch files) ?
Is it:
A, "diff orig_file round_trip_file | wc -c" == 0
B, sort files by some program and there will be no diffs
C, converting files to jpg's and they they don't show any differences
D, the netlists produced with alt. orig/round_trip produces no diff
E, something else
For choise A, one could just include the whole orig_file in the verilog
file as a comment or something.
For B, I have a sorting program at:
http://aspodata.se/git/openhw/bin/sort_sch.pl and GedaSch.pm
yes, it needs testing.
For C, there is lepton-schdiff/schdiff.
About D, the unnamed nets might have different numberings.
>From what I understand from
https://archive.fosdem.org/2016/schedule/event/eda_data_interchange/
is that A is not required but D is.
Regards,
/Karl Hammar
- sym to verilog-ams, karl, 2022/04/03
- Re: sym to verilog-ams, Felix Salfelder, 2022/04/03
- Re: sym to verilog-ams, karl, 2022/04/04
- gnucap-geda, sym file hndling (was Re: sym to verilog-ams), karl, 2022/04/04
- Re: sym to verilog-ams,
karl <=
- Re: sym to verilog-ams, al davis, 2022/04/06
- Re: sym to verilog-ams, karl, 2022/04/14
Re: sym to verilog-ams, al davis, 2022/04/04
Re: sym to verilog-ams, al davis, 2022/04/04