Re: sym to verilog-ams

[Felix Salfelder]

On Sun, Apr 03, 2022 at 01:14:57PM +0200, karl@aspodata.se wrote:
> How do I conert a sym file to verilog ?
> 
> My conclusion is that it isn't meaningful to do automatic conversion 
> from sym file to verilog-ams file except perhaps for a first skeleton
> containing the port names used.
> 
> And for a first skeleton, should a converter use the pinseq, pinnumber 
> or the pinlabel attribute for the ports ?

It's much the same as schematics. geda has top level objects, and
verilog doesn't, so you put everything into a module definition. The
goal is to reproduce the sym file back from its verilog representation
(round-trip).

In the schematic tests, I use the "list" command, and "list main" prints
the main module definition (in verilog mode) and the contents of the
schematic (in geda language mode) respectively.

gnucap-geda has an ad-hoc symbol implementation in src/symbol.h dating
back to 2012. It sort of serves the purpose, but it must be implemented
correctly.

- GEDA_SYMBOL must become a plugin.
   either use subckt from d_subckt.cc, or something similar derived from
        BASE_SUBCKT
- The parser in GEDA_SYMBOL::GEDA_SYMBOL must be singled out.
- GEDA_PIN must be a plugin as well.
- GEDA_SYMBOL_MAP, where libgeda is (ab)used, must be dropped.
   (this is strictly off-topic.)

cheers
felix