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Re: geda/lepton schematics

From: Felix Salfelder
Subject: Re: geda/lepton schematics
Date: Sun, 27 Mar 2022 13:21:56 +0200

On Sun, Mar 27, 2022 at 12:53:46PM +0200, wrote:
> Felix:
> ...
> > Lepton people should store connectivity in their schematic files. Then,
> > their schematic files would be much closer to structural Verilog (to an
> > extent that they could just consider to use Verilog instead).
> ...
> I don't think that that is possible in a design with subsheets (why is 
> hierarchical so hard to spell, I need a better name for it).

A subsheet is essentially a subcircuit macro. It exists in spice
(.subckt) and in Verilog ("module" with sub-components), and in the
others as well.

Such a macro has ports, internal nets, parameters and a list of
components + the connectivity (!). Much the same as a schematic
subsheet, just without the positions.

Think of it in this way or the other.

This way: The Verilog standard defines variables for positions
($xposition and $yposition). Set the device positions in a Verilog macro
module, and obtain a schematic.

The other way: take a gEDA schematic, make connections explicit, and
find a way to store it (try Verilog?).

> If you only have nets and symbols, the full connectivity is contained
> in just one file and could just as well be listed there.

You are suggesting to flatten the net. Why do you need that? Once you
have lost the hierarchy, there is no way to recover it.

> But if you have a subsheet, say a dc-dc converter with a source symbol
> that says
>  pin  label
>  1    Vin
>  2    GND
>  3    Vout
> then that could refer to anything from a resistor+zener, 7805 to some

There are circuits with subsheets in some gnucap-geda/{examples,tests}/*
(I am sure they lack documentation and instructions.)


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