possible nested modules bug

[Felix Salfelder]

Hi Al.

Some playing with translations revealed this one. It looks like a bug to
me.

"""
verilog

module m0( a b );
endmodule

module test0( a b );
   m0 #() mm( a b ); // OK
endmodule

module main( a b );
   module m1( a b );
   endmodule

   module test1( a b );
      m1 #() mm( a b ); // error: m1: no match
   endmodule
endmodule
"""

The "module" command in lang_verilog.cc replicates the ".subckt" command
in lang_spice.cc. First of all, the latter is working as expected when
using a spice version of the above circuit.

The relevant difference between spice and verilog subcircuit
instances... Spice has an X pseudo device, and verilog doesn't. The
attempt to resolve m1 fails, because test1 does not have an owner at the
time. Note how m0 is found, falling back to the questionable global root
scope.

Setting the owner of test1 to main before parsing m1 looks like a
workaround. It may lead to more issues. Please let me know if you have
better plans.

thanks
felix