Re: gnucap verilog syntax

[Felix Salfelder]

On Mon, Aug 03, 2020 at 11:19:37AM +0200, patrick wrote:
> Do you have reference to the Verilog syntax that Gnucap supports?

Gnucap has an example verilog module. you could change it to anything
you need, I don't know if the capabilities are fully documented, but the
code itself is quite human readable and straightforward. we have tests,
in tests/lang_verilog.*.gc.

there is an experimental ('hacked') verilog module, that can do some
more, esp. preprocessing, in gnucap-custom. it comes with tests, too.

if something essential is missing, please let us know.

> I have a Spice netlist somewhere, maybe i could try it first.

it is possible to combine spice and verilog subckts/modules in an
arbitary way. there is a section about it somewhere in the wiki. a
pitfall -- spice is case insensitive by default, and all input is
interpreted as upper case in spice mode. you may do ".options
noinsensitive" after switching to spice (qucsator has lots of this in
the component library), or use upper case identifiers.

cheers
felix