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Re: modelgen & veriloga
Re: modelgen & veriloga
Tue, 25 Feb 2020 15:01:04 +0100
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Hi Felix, many thanks for the detailed answer!
Le 2/25/20 à 2:01 PM, Felix Salfelder a écrit :
I'm aware of that :) I would target verilog-a 1st to get compact models
Verilog-ADMS only contains a subset of Verilog-A, and adds other things.
Verilog-AMS is a superset of Verilog-A,
and gnucap has been designed with mixed signal in mind.
then extend to AMS.
Simulation speed rapidly matters, so we should directly go with
The spice templates produce code that computes matrix stamps and current
contributions. These represent voltage controlled current sources, and
there is considerable overhead in the templates that relates to
"ddx" is where I gave up -- it was not fun anymore, when
changes to adms internals were required.
What we really need to break the deadlock is
Is there anything existing beyond an empty repository?
I suggest to implement it one step at a time
and reuse as much as possible. In a nutshell that is
- a simple verilog parser. like mg_in.cc (to grow as/where needed).
lex/yacc looks compelling, but it can be a can of worms.
I had seen that yosis parses verilog with lex/yacc rules; however I have
read that these tools also produce quite heavy code.
Currently, lang_verilog doesn't use anything external? I'm balancing
between not re-inventing and not over-engineering thing...
So we would go for a "subcircuit" architecture, not trying to plug
directly into matrix? I understand it is more generic & flexible, is it
- make a subcircuit with components in it, and deal with parameters.
relatively straightforward, but helps with understanding gnucap.
(carefully avoid MODEL_CARD)
- implement some Expression infrastructure (c.f. m_expression.h)
we need some derivatives and dependency tracking. partly nontrivial.
What do you mean with "dependency"?
- eject components for @analog block. much like modelgen. perhaps use
or recycle the voltage and current sources from gnucap-adms.
You mean pass over "subckt" instances?
- support dynamic expressions, ddt/idt/ddx
likely more nontrivial, but this is what you need for "verilog-A".
- (whatever I forgot)
- disciplines, logic blocks, connect modules, cross events
intersects with other work in progress. only a matter of time.
Finish line not in direct sight :)
- make it run faster, in many ways.
Faster than what? ADMS?
Certainly a challenge. I am happy to discuss details. Please feel free
to ask. Al might have more to say about it.
Many thanks again!