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modelgen & veriloga

From: Vincent Pinon
Subject: modelgen & veriloga
Date: Tue, 25 Feb 2020 00:51:46 +0100


I would like to simulate Analog(+MS) IC designs with recent compact models 
(PSP103, BSIM-IMG), which are delivered as VerilogA code.
On commercial programs, I also often drive my simulations with Verilog-A(MS) 

Running these in gnucap would be really cool :)

I have read on your site that ADMS seems sort of a dead-end to load VerilogA 
code, which I agree after struggling to get these models understood by the 
NGspice back-end (with no success)!
I read you were thinking of evolving your modelgen tool for this kind of task, 
unfortunately the gnucap-modelgen-verilog repository on savannah is empty.

I am thinking of spending some time on this for the months to come (I already 
know analog simulation & C++ quite well)
Do you have any pointer to help me to start? Code, discussions, advice, ideas...

Cheers and thanks for your work!


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