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Re: [Gnucap-devel] max_nodes, net_nodes

From: al davis
Subject: Re: [Gnucap-devel] max_nodes, net_nodes
Date: Mon, 22 Sep 2014 21:12:56 -0400
User-agent: KMail/1.13.7 (Linux/3.2.0-4-amd64; KDE/4.8.4; x86_64; ; )

As basis .. refererence the documentation:

On Monday 22 September 2014, Felix Salfelder wrote:
> do you agree? anything else maybe?

> - change max_nodes() in DEV_SUBCKT to
>   {if(_parent){ return _parent->net_nodes();}else{return

Maybe.  Let me think about it.

> - change the asertion in
> COMPONENT::port_value(int) to assert(i < max_nodes());

Maybe.  Let me think about it.

> const std::string COMPONENT::port_value(int i)const
> {
>   assert(_n);
>   assert(i >= 0);
>   assert(i < net_nodes()); // <- boom
>   return _n[i].short_label();
> }

This code is correct.

i >= net_nodes() is not valid here.

Higher values of i may be allocated, but short_label does not 
contain anything meaningful.

> std::string DEV_SUBCKT::port_name(int i)const {
>   if (_parent) {
>     return _parent->port_value(i);
>   }else{itested();
>     return "";
>   }
> }
> here, _parent is a MODEL_SUBCKT where port_value comes from
> COMPONENT, but...

if (_parent) {
  // it is known what the _parent is
  // it is not known what the _parent is, 
  // or even if there is one.
  // the statement being parsed may be incorrect 
  // but we don't know yet.

> std::string DEV_SUBCKT::port_name(int i)const {
>   if (_parent) {
>     return _parent->port_value(i);
>   }else{itested();
>     return "";
>   }
> }

Same comment as above.

> in COMPONENT::set_port_by_name, there is a call to
> port_name(i) in
> for (int i=0; i<max_nodes(); ++i) {
> [..]
> }

void COMPONENT::set_port_by_name(std::string& int_name, 
std::string& ext_name)
  for (int i=0; i<max_nodes(); ++i) {itested();
    if (int_name == port_name(i)) {itested();
      set_port_by_index(i, ext_name);
  throw Exception_No_Match(int_name);

This is used by verilog, not spice, setting ports by name, a 
feature that spice doesn't have.  Verilog requires a "module" 
definition before one can be instantiated.  Spice does not 
require the ".subckt" before the "X" line.

So, for a DEV_SUBCKT, in Verilog, _parent is always true here.

Again .....

> - change max_nodes() in DEV_SUBCKT to
>   {if(_parent){ return _parent->net_nodes();}else{return

I think you are correct.  The max_nodes() of the offspring is 
the actual net_nodes() of the parent.

Should min_nodes should also change?
   {if(_parent){ return _parent->net_nodes();}else{return 0;}} 
Not sure ....  it would rule out variable port lists.
So ....  NO.

Expected side effects of the change ....

In Spice syntax, as it stands, a mismatch in port count between 
the "X" line and its ".subckt" declaration is not flagged as an 
error at read time.  After the change, some places it might 
catch this user error.

You didn't post the test case.  My conclusion of what it was 
....  In Verilog syntax, a user error, entering a node by name, 
with a name that doesn't exist.  It runs past the real end of 
the list searching for it.

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