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Re: [Gnucap-devel] commands in spectre mode.

From: Dan McMahill
Subject: Re: [Gnucap-devel] commands in spectre mode.
Date: Sat, 01 Dec 2007 09:58:36 -0500
User-agent: Mail/News (X11/20070512)

al davis wrote:

2. Are commands sequential, like normal gnucap commands, or
like mixed batch of cards, like spice?
sequential but the whole topology of the circuit is read in
first.  i.e. you can put your analysis commands before the
circuit netlist if you  want.

Good, except for the "but" part. I regularly use the gnucap feature to partly build a circuit, simulate, build more ... unbuild some, simulate ...

What about interactive operation? .. typing in commands and components from the keyboard?

there seems to be some capability, but I've never used it. google 'spectre manual'.

3. How to set up probes?
you'll find stuff like this:

finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
saveOptions options save=allpub

These statements control things like what is written out and
what signals are saved.

Can you explain?  I don't understand.

Note that as with everything else the first field is the instance name and is arbitrary.

Most of those are instances of 'info'. Info can write out things like your model parameters, input parameters, output parameters, operating point parameters, etc. The last is an instance of 'options' save=allpub means all node voltages are written out to the results files for each sim. You can also use save=selected and then have an instance of 'save' that specifies which voltages and currents are saved. There are other options for saving currents and signals which are internal to verilog-A modules.

I have seen commands like:
foo (a b c) tran start=0 stop=1u

Which looks like a decent way to spec node probes, but what about other probes?

I think, but am not 100% sure, that basically your hooks are the save parameter to an options instance and then using the save instance to specify what is saved.

4. Are there order requirements?  For example, is it
necessary to have a "model" before its instance?  Do
commands need to be after the circuit is described?
commands may come before the circuit is described.  It
appears that it must read the whole netlist once to get the
circuit and then goes throuh again to do the commands.

That is easy to do.  What about interactive mode?

I really have no ideal about the capability in interactive mode. Until today I didn't even know spectre had one.

subcircuits can be instantiated before they are defined.  I
*think* the same is true for models.

gnucap does this now.

5. Can you have model within subckt?  subckt within subckt?
yes, yes.  They have subckt scope then.

gnucap does this now, but not in Verilog mode. Should the Verilog mode allow this as a non-standard extension? (and pressure the committee to add it to the standard?)

hmmm. I have mixed feeling about adding a non-standard extension. That said, it seems like modules with module scope have some advantage. I think you could probably come up with arguments to sway me in either direction.

You can also put analysis instances in a subcircuit.  for

// define the circuit

// define some sims we'd like to run
subckt mysims
ac1 ac start=1k stop=10e6 dec=25
tran1 tran start=0 stop=10u
ends mysims

// run the sims
mysims1 mysims

I like that.

it is pretty neat.

// modify some value
alter1 alter <rest of alter statement>

Can you say more about alter?

an 'alter' instance will change the value of a model parameter, a subcircuit parameter, a global parameter, temperature, or an instance parameter. So if you want to simulate, change temperature, and resimulate:

mysim1 mysim
alter1 alter param=temp value=50
mysim2 mysim
alter2 alter param=temp value=75
mysim3 mysim


Say you want to change bf on a bipolar model for all instances of the model:

alter1 alter mod=mymodel param=bf value=50

// rerun the sims
mysims2 mysims

This will give results files called mysims1.ac1,
mysims1.tran1, mysims2.ac1, mysims2.tran1

or is it "" ?

I stand corrected.  It is what you say.

6. What other questions should I be asking?

// include a section from a file
include "/some/model/file" section=<mysection>

How are sections marked?  By a section do you mean a subckt?

sections are marked with section/endsection. Not a subckt but rather just a specific subset of a file. Maybe an example is more clear, here is a bare bones library that has fast/nom/slow process corners for a process with 1 resistor and 1 capacitor type.


library mycornerlib

section nom
parameter rsheet=100
parameter carea=10
include "myfile.scs" section=models
endsection nom

section fast
parameter rsheet=80
parameter carea=8.5
include "myfile.scs" section=models
endsection fast

section slow
parameter rsheet=120
parameter carea=11.5
include "myfile.scs" section=models
endsection fast

section models

subckt myresistor a b
parameters squares=1
r1 (a b) resistor r=squares*rsheet
ends myresistor

subckt mycap a b
parameters area=1
c1 (a b) capacitor c=area*carea
ends mycap

endsection models

endlibrary mycornerlib

Now in your main netlist, you can include your model library with

include "mylib.scs" section=nom


include "mylib.scs" section=fast

to get different process corners.


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