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Re: [Gnucap-devel] commands in spectre mode.

From: al davis
Subject: Re: [Gnucap-devel] commands in spectre mode.
Date: Sat, 1 Dec 2007 01:51:05 -0500
User-agent: KMail/1.9.7

On Friday 30 November 2007, Dan McMahill wrote:
> > 1. When a command is prefixed with an instance name, what
> > to do with the name?
> Spectre uses it to name the results files.  For example
> tran1 tran start=0 stop=1u ....
> tran2 tran start=1u stop=2u
> mysim ac ....
> will produce results files called "tran1.tran", "tran2.tran",
> "".

Equivalent to gnucap:
tran 0 1u >tran1.tran

I need to add the names "start" "stop" ...  It adds one line of 
code for each.

> commands are in fact instances just like elements (except
> their order of appearance matters)

Like gnucap.

> > 2. Are commands sequential, like normal gnucap commands, or
> > like mixed batch of cards, like spice?
> sequential but the whole topology of the circuit is read in
> first.  i.e. you can put your analysis commands before the
> circuit netlist if you  want.

Good, except for the "but" part.  I regularly use the gnucap 
feature to partly build a circuit, simulate, build more ... 
unbuild some, simulate ...

What about interactive operation? .. typing in commands and 
components from the keyboard?

> > 3. How to set up probes?
> you'll find stuff like this:
> finalTimeOP info what=oppoint where=rawfile
> modelParameter info what=models where=rawfile
> element info what=inst where=rawfile
> outputParameter info what=output where=rawfile
> designParamVals info what=parameters where=rawfile
> saveOptions options save=allpub
> These statements control things like what is written out and
> what signals are saved.

Can you explain?  I don't understand.

I have seen commands like:
foo (a b c) tran start=0 stop=1u

Which looks like a decent way to spec node probes, but what 
about other probes?

> > 4. Are there order requirements?  For example, is it
> > necessary to have a "model" before its instance?  Do
> > commands need to be after the circuit is described?
> commands may come before the circuit is described.  It
> appears that it must read the whole netlist once to get the
> circuit and then goes throuh again to do the commands.

That is easy to do.  What about interactive mode?

> subcircuits can be instantiated before they are defined.  I
> *think* the same is true for models.

gnucap does this now.

> > 5. Can you have model within subckt?  subckt within subckt?
> yes, yes.  They have subckt scope then.

gnucap does this now, but not in Verilog mode.  Should the 
Verilog mode allow this as a non-standard extension?  (and 
pressure the committee to add it to the standard?)

> You can also put analysis instances in a subcircuit.  for
> example
> // define the circuit
> // define some sims we'd like to run
> subckt mysims
> ac1 ac start=1k stop=10e6 dec=25
> tran1 tran start=0 stop=10u
> ends mysims
> // run the sims
> mysims1 mysims

I like that.

> // modify some value
> alter1 alter <rest of alter statement>

Can you say more about alter?

> // rerun the sims
> mysims2 mysims
> This will give results files called mysims1.ac1,
> mysims1.tran1, mysims2.ac1, mysims2.tran1

or is it "" ?

> > 6. What other questions should I be asking?
> // define certain nodes to have global scope
> global <list of nodes>
> // list of parameters.  Can be at the "top" level or within a
> subckt parameters <var1>=<default1> <var2>=<default2>

need to add at top.

> // include the entire contents of a file
> // specte can do "~" expansion
> include "/path/to/myfile"

got that

> // include a section from a file
> include "/some/model/file" section=<mysection>

How are sections marked?  By a section do you mean a subckt?

> includes can be nested, i.e. an included file can include
> other files, it can even include other sections of itself. 
> Included files act just like #include in C (i.e., it is like
> you pasted the contents in)

> // include a verilog-A file
> ahdl_include "/path/to/"

Gnucap "attach" (what it will be when finished).

> subcircuits (and probably the top level circuit) can have
> conditionals that affect the circuit topology:
> subckt myckt a b
> parameters p=0
> if( p==0)
> R1 (a b) resistor r=1k
> else
> L1 (a b) inductor l=1u
> endif
> ends myckt
> Lseries (in out) myckt p=0
> Rshunt (out gnd) myckt p=1

need to add "if" "else" ... not just for this.

> you can use this notation too
> value=(p==1 ? <val1> : <val2>)

Need to finish expression evaluation.  I have code, just need to 
move it.

> I'm sure there must be more you care about.

That is good for now.  More will come out in time.


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