[Emacs-diffs] master 99a7a18: Fix indentation of default clocking definitions.

[Wilson Snyder]

branch: master
commit 99a7a188ec052ffcae06ffe49ffe29ccbc2c50ee
Author: Wilson Snyder <address@hidden>
Commit: Wilson Snyder <address@hidden>

    Fix indentation of default clocking definitions.
    
    * verilog-mode.el (verilog-default-clocking-re): Fix indentation of default
    clocking definitions, Verilog-Mode bug1457. Reported by Paul Donahue.
---
 lisp/progmodes/verilog-mode.el | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el
index 8ddd262..a914724 100644
--- a/lisp/progmodes/verilog-mode.el
+++ b/lisp/progmodes/verilog-mode.el
@@ -121,7 +121,7 @@
 ;;
 
 ;; This variable will always hold the version number of the mode
-(defconst verilog-mode-version "2019-05-06-28bee25-vpo-GNU"
+(defconst verilog-mode-version "2019-06-21-626dba1-vpo-GNU"
   "Version of this Verilog mode.")
 (defconst verilog-mode-release-emacs t
   "If non-nil, this version of Verilog mode was released with Emacs itself.")
@@ -2910,7 +2910,7 @@ find the errors."
     
"\\(\\<\\(import\\|export\\)\\>\\s-+\"DPI\\(-C\\)?\"\\s-+\\(\\<\\(context\\|pure\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\\)?\\<\\(function\\|task\\)\\>\\)"
     ))
 
-(defconst verilog-default-clocking-re "\\<default\\s-+clocking\\>")
+(defconst verilog-default-clocking-re 
"\\<default\\s-+clocking\\s-+[A-Za-z_][A-Za-z0-9_]*\\s-*;")
 (defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
 (defconst verilog-extended-case-re 
"\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\|randcase\\)")
 (defconst verilog-extended-complete-re
@@ -11524,6 +11524,11 @@ See `verilog-auto-star' for more information.
 The pins are printed in declaration order or alphabetically,
 based on the `verilog-auto-inst-sort' variable.
 
+To debug what file a submodule comes from, in a buffer with
+AUTOINST, use \\[verilog-goto-defun] to switch buffers to the
+point containing the given symbol (i.e. a submodule name)'s
+module definition.
+
 Limitations:
   Module names must be resolvable to filenames by adding a
   `verilog-library-extensions', and being found in the same directory, or