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[dotgnu-pnet-commits] [SCM] DotGNU Portable.NET engine, compilers and to
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From: |
Klaus Treichel |
|
Subject: |
[dotgnu-pnet-commits] [SCM] DotGNU Portable.NET engine, compilers and tools (pnet) branch, master, updated. 1b86b6f9201060672dccd0f8e7b7b79c3c76817a |
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Date: |
Wed, 07 Apr 2010 09:35:35 +0000 |
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- Log -----------------------------------------------------------------
http://git.savannah.gnu.org/cgit/pnet.git/commit/?id=1b86b6f9201060672dccd0f8e7b7b79c3c76817a
commit 1b86b6f9201060672dccd0f8e7b7b79c3c76817a
Author: Klaus Treichel <address@hidden>
Date: Wed Apr 7 11:35:11 2010 +0200
Add more floatingpoint support for the cvm unroller.
diff --git a/ChangeLog b/ChangeLog
index d5dc344..23c4a59 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -4,6 +4,28 @@
* engine/cvm_call.c: Remove the code for the COP_CCTOR_ONCE opcode.
+ * engine/amd64_codegen.h: Add memindex addressing macros for fld and
+ fst opcodes.
+
+ * engine/x86_codegen.h: Add memindex addressing macros for fld and
+ fst opcodes.
+
+ * engine/md_amd64.c: Some reformatting.
+
+ * engine/md_amd64.h: Add conversion macros from signed and unsigned
+ 32 bit and signed 64 bit integer values to floats.
+ Add macros for loading and storing floatingpoint values from/to arrays.
+
+ * engine/unroll.c (GetTopTwoWordAndFPRegisters): Function added for
+ floatingpoint array stores.
+
+ * engine/unroll_conv.c (COP_I2F, COP_IU2F, COP_L2F, COP_LU2F): Add
+ unroller support for these cvm opcodes.
+
+ * engine/unroll_ptr.c (COP_PREFIX_FREAD_ELEM, COP_PREFIX_DREAD_ELEM,
+ COP_PREFIX_FWRITE_ELEM, COP_PREFIX_DWRITE_ELEM): Add unroller support
+ for these cvm opcodes.
+
2010-04-06 Klaus Treichel <address@hidden>
* engine/amd64_codegen.h: Remove emitting the Rex prefix for some fpu
diff --git a/engine/amd64_codegen.h b/engine/amd64_codegen.h
index 550f244..72bb5e3 100644
--- a/engine/amd64_codegen.h
+++ b/engine/amd64_codegen.h
@@ -435,6 +435,11 @@ typedef union {
amd64_membase_emit ((inst), 0, (basereg), (disp)); \
} while (0)
+#define amd64_fld_memindex(inst,basereg,disp,indexreg,is_double) do { \
+ amd64_emit_rex ((inst),0,0,(indexreg),(basereg)); \
+ x86_fld_memindex((inst),((basereg)
&0x7),(disp),((indexreg)&0x7),(is_double)); \
+} while (0)
+
#define amd64_call_membase_size(inst,basereg,disp,size) do { amd64_emit_rex
((inst),0,0,0,(basereg)); *(inst)++ = (unsigned char)0xff; amd64_membase_emit
((inst),2, (basereg),(disp)); } while (0)
/*
@@ -633,8 +638,9 @@ typedef union {
#define amd64_fldz_size(inst,size) do { amd64_emit_rex ((inst),0,0,0,0);
x86_fldz(inst); } while (0)
#define amd64_fld1_size(inst,size) do { amd64_emit_rex ((inst),0,0,0,0);
x86_fld1(inst); } while (0)
#define amd64_fldpi_size(inst,size) do { amd64_emit_rex ((inst),0,0,0,0);
x86_fldpi(inst); } while (0)
-#define amd64_fst_size(inst,mem,is_double,pop_stack,size) do { amd64_emit_rex
((inst),0,0,0,0); x86_fst((inst),(mem),(is_double),(pop_stack)); } while (0)
-#define amd64_fst_membase_size(inst,basereg,disp,is_double,pop_stack,size) do
{ amd64_emit_rex ((inst),0,0,0,(basereg));
x86_fst_membase((inst),((basereg)&0x7),(disp),(is_double),(pop_stack)); } while
(0)
+#define amd64_fst(inst,mem,is_double,pop_stack) do { amd64_emit_rex
((inst),0,0,0,0); x86_fst((inst),(mem),(is_double),(pop_stack)); } while (0)
+#define amd64_fst_membase(inst,basereg,disp,is_double,pop_stack) do {
amd64_emit_rex ((inst),0,0,0,(basereg));
x86_fst_membase((inst),((basereg)&0x7),(disp),(is_double),(pop_stack)); } while
(0)
+#define amd64_fst_memindex(inst,basereg,disp,indexreg,is_double,pop_stack) do
{ amd64_emit_rex ((inst),0,0,(indexreg),(basereg));
x86_fst_memindex((inst),((basereg)&0x7),(disp),((indexreg)&0x7),(is_double),(pop_stack));
} while (0)
#define amd64_fst80_mem_size(inst,mem,size) do { amd64_emit_rex
((inst),0,0,0,0); x86_fst80_mem((inst),(mem)); } while (0)
#define amd64_fst80_membase_size(inst,basereg,disp,size) do { amd64_emit_rex
((inst),0,0,0,(basereg)); x86_fst80_membase((inst),((basereg)&0x7),(disp)); }
while (0)
#define amd64_fist_pop_size(inst,mem,is_long,size) do { amd64_emit_rex
((inst),0,0,0,0); x86_fist_pop((inst),(mem),(is_long)); } while (0)
@@ -838,8 +844,6 @@ typedef union {
#define amd64_fldz(inst) amd64_fldz_size(inst,8)
#define amd64_fld1(inst) amd64_fld1_size(inst,8)
#define amd64_fldpi(inst) amd64_fldpi_size(inst,8)
-#define amd64_fst(inst,mem,is_double,pop_stack)
amd64_fst_size(inst,mem,is_double,pop_stack,8)
-#define amd64_fst_membase(inst,basereg,disp,is_double,pop_stack)
amd64_fst_membase_size(inst,basereg,disp,is_double,pop_stack,8)
#define amd64_fst80_mem(inst,mem) amd64_fst80_mem_size(inst,mem,8)
#define amd64_fst80_membase(inst,basereg,disp)
amd64_fst80_membase_size(inst,basereg,disp,8)
#define amd64_fist_pop(inst,mem,is_long)
amd64_fist_pop_size(inst,mem,is_long,8)
diff --git a/engine/md_amd64.c b/engine/md_amd64.c
index 75ea43f..8e7154b 100644
--- a/engine/md_amd64.c
+++ b/engine/md_amd64.c
@@ -79,8 +79,8 @@ md_inst_ptr _md_amd64_mov_membase_reg_byte
}
md_inst_ptr _md_amd64_mov_memindex_reg_byte(md_inst_ptr inst, int basereg,
-
unsigned offset, int indexreg,
-
int srcreg)
+
unsigned offset, int indexreg,
+
int srcreg)
{
if(srcreg == AMD64_RAX || srcreg == AMD64_RBX ||
srcreg == AMD64_RCX || srcreg == AMD64_RDX)
diff --git a/engine/md_amd64.h b/engine/md_amd64.h
index ee00b34..55c4b78 100644
--- a/engine/md_amd64.h
+++ b/engine/md_amd64.h
@@ -337,7 +337,7 @@ md_inst_ptr _md_amd64_mov_membase_reg_byte
* floating-point stack.
*/
#define md_store_membase_float_32(inst,reg,basereg,offset) \
- amd64_fst_membase_size((inst), (basereg), (offset), 0,
1, 4)
+ amd64_fst_membase((inst), (basereg), (offset), 0, 1)
#define md_store_membase_float_64(inst,reg,basereg,offset) \
amd64_fst_membase((inst), (basereg), (offset), 1, 1)
#define md_store_membase_float_native(inst,reg,basereg,offset) \
@@ -503,6 +503,43 @@ extern md_inst_ptr _md_amd64_widen_byte(md_inst_ptr inst,
int reg, int isSigned)
} while (0)
/*
+ * Convert a signed 32 bit value in the general register to a native
+ * floating-point value an load it into the top fp register.
+ */
+#define md_conv_sword_32_float(inst,dreg,sreg) \
+ do { \
+ amd64_alu_reg_imm((inst), X86_SUB, AMD64_RSP,
8); \
+ amd64_mov_membase_reg((inst), AMD64_RSP, 0,
(sreg), 4); \
+ amd64_fild_membase((inst), AMD64_RSP, 0, 0); \
+ amd64_alu_reg_imm((inst), X86_ADD, AMD64_RSP,
8); \
+ }while(0)
+
+/*
+ * Convert an unsigned 32 bit value in the general register to a native
+ * floating-point value an load it into the top fp register.
+ */
+#define md_conv_uword_32_float(inst,dreg,sreg) \
+ do { \
+ amd64_alu_reg_imm((inst), X86_SUB, AMD64_RSP,
8); \
+ amd64_mov_membase_reg((inst), AMD64_RSP, 0,
(sreg), 4); \
+ amd64_mov_membase_imm((inst), AMD64_RSP, 4, 0,
4); \
+ amd64_fild_membase((inst), AMD64_RSP, 0, 1); \
+ amd64_alu_reg_imm((inst), X86_ADD, AMD64_RSP,
8); \
+ }while(0)
+
+/*
+ * Convert a signed 64 bit value in the general register to a native
+ * floating-point value an load it into the top fp register.
+ */
+#define md_conv_sword_64_float(inst,dreg,sreg) \
+ do { \
+ amd64_alu_reg_imm((inst), X86_SUB, AMD64_RSP,
8); \
+ amd64_mov_membase_reg((inst), AMD64_RSP, 0,
(sreg), 8); \
+ amd64_fild_membase((inst), AMD64_RSP, 0, 1); \
+ amd64_alu_reg_imm((inst), X86_ADD, AMD64_RSP,
8); \
+ }while(0)
+
+/*
* Swap the top two items on the floating-point stack.
*/
#define md_freg_swap(inst) amd64_fxch((inst), 1)
@@ -738,6 +775,38 @@ extern md_inst_ptr _md_amd64_compare
} while (0)
/*
+ * Load a 32 bit floatingpoint value from an indexed array.
+ */
+#define md_load_memindex_float_32(inst,reg,basereg,indexreg,disp) \
+ do { \
+ amd64_fld_memindex((inst), (basereg), (disp),
(indexreg), 0); \
+ } while (0)
+
+/*
+ * Load a 64 bit floatingpoint value from an indexed array.
+ */
+#define md_load_memindex_float_64(inst,reg,basereg,indexreg,disp) \
+ do { \
+ amd64_fld_memindex((inst), (basereg), (disp),
(indexreg), 1); \
+ } while (0)
+
+/*
+ * Store a 32 bit floatingpoint value to an indexed array.
+ */
+#define md_store_memindex_float_32(inst,reg,basereg,indexreg,disp) \
+ do { \
+ amd64_fst_memindex((inst), (basereg), (disp),
(indexreg), 0, 1); \
+ } while (0)
+
+/*
+ * Store a 64 bit floatingpoint value to an indexed array.
+ */
+#define md_store_memindex_float_64(inst,reg,basereg,indexreg,disp) \
+ do { \
+ amd64_fst_memindex((inst), (basereg), (disp),
(indexreg), 1, 1); \
+ } while (0)
+
+/*
* Store a 32-bit word value into an indexed array.
*/
#define md_store_memindex_word_32(inst,reg,basereg,indexreg,disp)
\
diff --git a/engine/unroll.c b/engine/unroll.c
index 765cd09..be8561b 100644
--- a/engine/unroll.c
+++ b/engine/unroll.c
@@ -1248,6 +1248,87 @@ static void GetFPAndWordRegisters(MDUnroll *unroll, int
*reg1, int *reg2)
#endif
}
+/*
+ * Get the three top-most stack values in two word and a FP register.
+ * "reg1" will be the lowest of the three.
+ */
+static void GetTopTwoWordAndFPRegisters(MDUnroll *unroll,
+
int *reg1, int *reg2,
+
int *reg3, int flags)
+{
+ /* Clear the cached local information */
+ unroll->cachedLocal = -1;
+ unroll->cachedReg = -1;
+
+ /* See if we already have two word and one fp register in play */
+ if(unroll->pseudoStackSize > 2)
+ {
+ *reg1 = unroll->pseudoStack[unroll->pseudoStackSize - 3];
+ if(!MD_IS_FREG(*reg1))
+ {
+ *reg2 = unroll->pseudoStack[unroll->pseudoStackSize -
2];
+ if(!MD_IS_FREG(*reg2))
+ {
+ *reg3 =
unroll->pseudoStack[unroll->pseudoStackSize - 1];
+ if(MD_IS_FREG(*reg3))
+ {
+ *reg1 &= ~MD_NATIVE_REG_MASK;
+ *reg2 &= ~MD_NATIVE_REG_MASK;
+ return;
+ }
+ }
+ }
+ }
+
+ /* See if we have one FP and one word registers in play */
+ if(unroll->pseudoStackSize == 2)
+ {
+ *reg2 = unroll->pseudoStack[0];
+ *reg3 = unroll->pseudoStack[1];
+ if(!MD_IS_FREG(*reg2) && MD_IS_FREG(*reg3))
+ {
+ *reg1 = RollRegisterStack(unroll, flags &
MD_REG1_NATIVE, -1);
+ *reg2 &= ~MD_NATIVE_REG_MASK;
+ return;
+ }
+ }
+
+ /* See if we have one FP register in play */
+ if(unroll->pseudoStackSize == 1)
+ {
+ *reg3 = unroll->pseudoStack[0];
+ if(MD_IS_FREG(*reg3))
+ {
+ *reg2 = RollRegisterStack(unroll, flags &
MD_REG2_NATIVE, -1);
+ *reg1 = RollRegisterStack(unroll, flags &
MD_REG1_NATIVE, -1);
+ return;
+ }
+ }
+
+ /* Flush the register stack and then reload into MD_REG_0, MD_REG_1 and
MD_FREG_0 */
+ FlushRegisterStack(unroll);
+ *reg1 = MD_REG_0;
+ *reg2 = MD_REG_1;
+ *reg3 = MD_FREG_0;
+ unroll->pseudoStack[0] = MD_REG_0 | MD_NATIVE_REG_MASK;
+ unroll->pseudoStack[1] = MD_REG_1 | MD_NATIVE_REG_MASK;
+ unroll->pseudoStack[2] = MD_FREG_0;
+ unroll->pseudoStackSize = 3;
+ unroll->stackHeight -= (CVM_WORDS_PER_NATIVE_FLOAT + 2) *
sizeof(CVMWord);
+ md_load_membase_word_native(unroll->out, MD_REG_0, MD_REG_STACK,
+ unroll->stackHeight);
+ md_load_membase_word_native(unroll->out, MD_REG_1, MD_REG_STACK,
+ unroll->stackHeight +
sizeof(CVMWord));
+ md_load_membase_float_native(unroll->out, MD_FREG_0, MD_REG_STACK,
+
unroll->stackHeight + 2 * sizeof(CVMWord));
+ unroll->regsUsed |= ((1 << MD_REG_0) | (1 << MD_REG_1));
+#if MD_FP_STACK_SIZE != 0
+ ++(unroll->fpStackSize);
+#else
+ unroll->regsUsed |= (1 << MD_FREG_0);
+#endif
+}
+
#endif /* MD_HAS_FP */
/*
diff --git a/engine/unroll_conv.c b/engine/unroll_conv.c
index 9beac3b..857baf2 100644
--- a/engine/unroll_conv.c
+++ b/engine/unroll_conv.c
@@ -62,6 +62,88 @@ break;
#ifdef MD_HAS_FP
+#ifdef md_conv_sword_32_float
+
+case COP_I2F:
+{
+ /* Read a float32 value from a pointer */
+ UNROLL_START();
+ CheckFPFull(&unroll);
+ reg = GetTopWordRegister(&unroll, MD_REG1_32BIT);
+ reg2 = GetFPRegister(&unroll);
+ md_conv_sword_32_float(unroll.out, reg2, reg);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ PushRegister(&unroll, reg2, 0);
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+}
+break;
+
+#endif /* md_conv_sword_32_float */
+
+#ifdef md_conv_uword_32_float
+
+case COP_IU2F:
+{
+ /* Read a float32 value from a pointer */
+ UNROLL_START();
+ CheckFPFull(&unroll);
+ reg = GetTopWordRegister(&unroll, MD_REG1_32BIT);
+ reg2 = GetFPRegister(&unroll);
+ md_conv_uword_32_float(unroll.out, reg2, reg);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ PushRegister(&unroll, reg2, 0);
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+}
+break;
+
+#endif /* md_conv_uword_32_float */
+
+#ifdef md_conv_sword_64_float
+
+/*
+ * TODO: Handle 32 bit archs.
+ */
+case COP_L2F:
+{
+ /* Read a float32 value from a pointer */
+ UNROLL_START();
+ CheckFPFull(&unroll);
+ reg = GetTopWordRegister(&unroll, MD_REG1_NATIVE);
+ reg2 = GetFPRegister(&unroll);
+ md_conv_sword_64_float(unroll.out, reg2, reg);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ PushRegister(&unroll, reg2, 0);
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+}
+break;
+
+#endif /* md_conv_sword_64_float */
+
+#ifdef md_conv_uword_64_float
+
+/*
+ * TODO: Handle 32 bit archs.
+ */
+case COP_LU2F:
+{
+ /* Read a float32 value from a pointer */
+ UNROLL_START();
+ CheckFPFull(&unroll);
+ reg = GetTopWordRegister(&unroll, MD_REG1_NATIVE);
+ reg2 = GetFPRegister(&unroll);
+ md_conv_uword_64_float(unroll.out, reg2, reg);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ PushRegister(&unroll, reg2, 0);
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+}
+break;
+
+#endif /* md_conv_uword_64_float */
+
case COP_F2F:
{
/* Truncate a floating point value to float32 */
diff --git a/engine/unroll_ptr.c b/engine/unroll_ptr.c
index 3f0d369..bf70844 100644
--- a/engine/unroll_ptr.c
+++ b/engine/unroll_ptr.c
@@ -1197,6 +1197,90 @@ case COP_PREAD_THIS:
}
break;
+#ifdef MD_HAS_FP
+
+#ifdef md_load_memindex_float_32
+
+case 0x100 + COP_PREFIX_FREAD_ELEM:
+{
+ /* Read a word from an array */
+ UNROLL_START();
+ GetTopTwoWordRegisters(&unroll, ®, ®2,
+ MD_REG1_NATIVE |
MD_REG2_32BIT);
+ reg3 = GetFPRegister(&unroll);
+ CheckArrayAccess(&unroll, reg, reg2, pc, (unsigned char *)inst);
+ md_load_memindex_float_32(unroll.out, reg3, reg, reg2, MD_ARRAY_HEADER);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ PushRegister(&unroll, reg3, 0);
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+}
+break;
+
+#endif /* md_load_memindex_float_32 */
+
+#ifdef md_load_memindex_float_64
+
+case 0x100 + COP_PREFIX_DREAD_ELEM:
+{
+ /* Read a word from an array */
+ UNROLL_START();
+ GetTopTwoWordRegisters(&unroll, ®, ®2,
+ MD_REG1_NATIVE |
MD_REG2_32BIT);
+ reg3 = GetFPRegister(&unroll);
+ CheckArrayAccess(&unroll, reg, reg2, pc, (unsigned char *)inst);
+ md_load_memindex_float_64(unroll.out, reg3, reg, reg2, MD_ARRAY_HEADER);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ PushRegister(&unroll, reg3, 0);
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+}
+break;
+
+#endif /* md_load_memindex_float_64 */
+
+#ifdef md_store_memindex_float_32
+
+case 0x100 + COP_PREFIX_FWRITE_ELEM:
+{
+ /* Read a word from an array */
+ UNROLL_START();
+ GetTopTwoWordAndFPRegisters(&unroll, ®, ®2, ®3,
+ MD_REG1_NATIVE
| MD_REG2_32BIT);
+ CheckArrayAccess(&unroll, reg, reg2, pc, (unsigned char *)inst);
+ md_store_memindex_float_32(unroll.out, reg3, reg, reg2,
MD_ARRAY_HEADER);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+}
+break;
+
+#endif /* md_store_memindex_float_32 */
+
+#ifdef md_store_memindex_float_64
+
+case 0x100 + COP_PREFIX_DWRITE_ELEM:
+{
+ /* Read a word from an array */
+ UNROLL_START();
+ GetTopTwoWordAndFPRegisters(&unroll, ®, ®2, ®3,
+ MD_REG1_NATIVE
| MD_REG2_32BIT);
+ CheckArrayAccess(&unroll, reg, reg2, pc, (unsigned char *)inst);
+ md_store_memindex_float_64(unroll.out, reg3, reg, reg2,
MD_ARRAY_HEADER);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ FreeTopRegister(&unroll, -1);
+ MODIFY_UNROLL_PC(CVM_LEN_NONE);
+}
+break;
+
+#endif /* md_store_memindex_float_64 */
+
+#endif /* MD_HAS_FP */
+
#ifdef MD_HAS_2D_ARRAYS
case 0x100 + COP_PREFIX_GET2D:
diff --git a/engine/x86_codegen.h b/engine/x86_codegen.h
index 7bea92e..98dbf52 100644
--- a/engine/x86_codegen.h
+++ b/engine/x86_codegen.h
@@ -1130,6 +1130,19 @@ typedef union {
x86_membase_emit ((inst), 0, (basereg), (disp)); \
} while (0)
+#define x86_fld_memindex(inst,basereg,disp,indexreg,is_double) \
+ do { \
+ *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned
char)0xd9; \
+ if(is_double) \
+ { \
+ x86_memindex_emit ((inst), 0, (basereg), (disp),
(indexreg), 3); \
+ } \
+ else \
+ { \
+ x86_memindex_emit ((inst), 0, (basereg), (disp),
(indexreg), 2); \
+ } \
+ } while (0)
+
#define x86_fld80_mem(inst,mem) \
do { \
*(inst)++ = (unsigned char)0xdb; \
@@ -1194,6 +1207,13 @@ typedef union {
x86_membase_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (basereg),
(disp)); \
} while (0)
+#define x86_fst_memindex(inst,basereg,disp,indexreg,is_double,pop_stack)
\
+ do { \
+ *(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned
char)0xd9; \
+ x86_memindex_emit ((inst), 2 + ((pop_stack) ? 1 : 0),
(basereg), (disp), \
+ (indexreg), ((is_double) ? 3
: 2)); \
+ } while (0)
+
#define x86_fst80_mem(inst,mem) \
do { \
*(inst)++ = (unsigned char)0xdb; \
@@ -1231,6 +1251,37 @@ typedef union {
} while (0)
/**
+ * @x86_fistt_pop (available only with SSE3)
+ * Same as x86_fist_pop except that the round towards zero mode is used.
+ */
+#define x86_fistt_pop(inst,mem,is_long) \
+ do { \
+ if ((is_long)) { \
+ *(inst)++ = (unsigned char)0xdd; \
+ x86_mem_emit ((inst), 1, (mem)); \
+ } else { \
+ *(inst)++ = (unsigned char)0xdb; \
+ x86_mem_emit ((inst), 1, (mem)); \
+ } \
+ } while (0)
+
+/**
+ * @x86_fistt_pop_membase (available only with SSE3)
+ * Same as x86_fist_pop_membase except that the round towards zero mode
+ * is used.
+ */
+#define x86_fistt_pop_membase(inst,basereg,disp,is_long) \
+ do { \
+ if ((is_long)) { \
+ *(inst)++ = (unsigned char)0xdd; \
+ x86_membase_emit ((inst), 1, (basereg), (disp));
\
+ } else { \
+ *(inst)++ = (unsigned char)0xdb; \
+ x86_membase_emit ((inst), 1, (basereg), (disp));
\
+ } \
+ } while (0)
+
+/**
* @x86_fist_membase
* Converts content of ST(0) to integer and stores it at memory location
* addressed by [basereg + disp].
-----------------------------------------------------------------------
Summary of changes:
ChangeLog | 22 ++++++++++++
engine/amd64_codegen.h | 12 ++++--
engine/md_amd64.c | 4 +-
engine/md_amd64.h | 71 ++++++++++++++++++++++++++++++++++++++++-
engine/unroll.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++
engine/unroll_conv.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++
engine/unroll_ptr.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++++
engine/x86_codegen.h | 51 +++++++++++++++++++++++++++++
8 files changed, 400 insertions(+), 7 deletions(-)
hooks/post-receive
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