[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[dotgnu-pnet-commits] libjit ChangeLog jit/jit-rules-arm.h jit/jit-ru...
|
From: |
Aleksey Demakov |
|
Subject: |
[dotgnu-pnet-commits] libjit ChangeLog jit/jit-rules-arm.h jit/jit-ru... |
|
Date: |
Mon, 23 Mar 2009 13:14:22 +0000 |
CVSROOT: /sources/dotgnu-pnet
Module name: libjit
Changes by: Aleksey Demakov <avd> 09/03/23 13:14:22
Modified files:
. : ChangeLog
jit : jit-rules-arm.h jit-rules-arm.c
Log message:
more mikyt's ARM code
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/libjit/ChangeLog?cvsroot=dotgnu-pnet&r1=1.410&r2=1.411
http://cvs.savannah.gnu.org/viewcvs/libjit/jit/jit-rules-arm.h?cvsroot=dotgnu-pnet&r1=1.9&r2=1.10
http://cvs.savannah.gnu.org/viewcvs/libjit/jit/jit-rules-arm.c?cvsroot=dotgnu-pnet&r1=1.24&r2=1.25
Patches:
Index: ChangeLog
===================================================================
RCS file: /sources/dotgnu-pnet/libjit/ChangeLog,v
retrieving revision 1.410
retrieving revision 1.411
diff -u -b -r1.410 -r1.411
--- ChangeLog 22 Mar 2009 21:33:27 -0000 1.410
+++ ChangeLog 23 Mar 2009 13:14:22 -0000 1.411
@@ -2,7 +2,8 @@
* jit/jit-gen-arm.h: add more ARM codegen macros including VFP
support.
- * jit/jit-rules-arm.ins: restore FPA rules.
+ * jit/jit-rules-arm.ins: restore ARM FPA rules.
+ * jit/jit-rules-arm.h, jit/jit-rules-arm.c: more ARM code.
2009-02-07 Aleksey Demakov <address@hidden>
Index: jit/jit-rules-arm.h
===================================================================
RCS file: /sources/dotgnu-pnet/libjit/jit/jit-rules-arm.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- jit/jit-rules-arm.h 24 Jan 2008 20:12:53 -0000 1.9
+++ jit/jit-rules-arm.h 23 Mar 2009 13:14:22 -0000 1.10
@@ -2,6 +2,7 @@
* jit-rules-arm.h - Rules that define the characteristics of the ARM.
*
* Copyright (C) 2004 Southern Storm Software, Pty Ltd.
+ * Copyright (C) 2008 Michele Tartara <address@hidden>
*
* This file is part of the libjit library.
*
@@ -30,26 +31,31 @@
#endif
/*
- * Determine if this ARM core has floating point registers available.
+ * Determine the kind of floating point unit that is being used (if any)
*/
-#if JIT_APPLY_NUM_FLOAT_REGS != 0 || JIT_APPLY_RETURN_FLOATS_AFTER != 0
- #define JIT_ARM_HAS_FLOAT_REGS 1
+#if defined(__VFP_FP__)
+/* Vector floating point unit (used by EABI systems) */
+# define JIT_ARM_HAS_VFP 1
+#elif defined(__FPA_FP__)
+/* Old floating point unit (used by OABI systems) */
+# define JIT_ARM_HAS_FPA 1
+#endif
+
+/*
+ * Determine if this ARM core uses floating point registers available
+ */
+#if defined(JIT_ARM_HAS_FPA) || defined(JIT_ARM_HAS_VFP)
+# define JIT_ARM_HAS_FLOAT_REGS 1
#endif
/*
* Information about all of the registers, in allocation order.
* We use r0-r5 for general-purpose values and r6-r8 for globals.
*
- * Of the floating-point registers, we only use f0-f3 at present,
- * so that we don't have to worry about saving the values of f4-f7.
* The floating-point registers are only present on some ARM cores.
+ *
+ * The definitions of the used flags are in jit-rules.h
*/
-#ifdef JIT_ARM_HAS_FLOAT_REGS
- #define JIT_REG_ARM_FLOAT \
- (JIT_REG_FLOAT32 | JIT_REG_FLOAT64 | JIT_REG_NFLOAT |
JIT_REG_CALL_USED)
-#else
- #define JIT_REG_ARM_FLOAT JIT_REG_FIXED
-#endif
#define JIT_REG_INFO \
{"r0", 0, 1, JIT_REG_WORD | JIT_REG_LONG | JIT_REG_CALL_USED}, \
{"r1", 1, -1, JIT_REG_WORD | JIT_REG_CALL_USED}, \
@@ -67,13 +73,84 @@
{"sp", 13, -1, JIT_REG_FIXED | JIT_REG_STACK_PTR}, \
{"lr", 14, -1, JIT_REG_FIXED}, \
{"pc", 15, -1, JIT_REG_FIXED}, \
+ JIT_REG_INFO_FLOAT_REGS
+
+/*
+ * Definitions in case of no floating point registers
+ */
+#ifndef JIT_ARM_HAS_FLOAT_REGS
+
+#define JIT_REG_INFO_FLOAT_REGS
+
+/* JIT_NUM_REGS is the total number of registers (general purpose) */
+#define JIT_NUM_REGS 16
+
+#endif /* JIT_ARM_HAS_FLOAT_REGS */
+
+/*
+ * Definitions in case of FPA
+ */
+#ifdef JIT_ARM_HAS_FPA
+
+#define JIT_REG_ARM_FLOAT \
+ (JIT_REG_FLOAT32 | JIT_REG_FLOAT64 | JIT_REG_NFLOAT | JIT_REG_CALL_USED)
+
+#define JIT_REG_INFO_FLOAT_REGS \
{"f0", 0, -1, JIT_REG_ARM_FLOAT}, \
{"f1", 1, -1, JIT_REG_ARM_FLOAT}, \
{"f2", 2, -1, JIT_REG_ARM_FLOAT}, \
{"f3", 3, -1, JIT_REG_ARM_FLOAT},
+
+/* JIT_NUM_REGS is the total number of registers (general purpose+floating
point) */
#define JIT_NUM_REGS 20
+
+#endif /* JIT_ARM_HAS_FPA */
+
+/*
+ * Definitions in case of VFP
+ */
+#ifdef JIT_ARM_HAS_VFP
+
+#define JIT_REG_ARM_FLOAT32 (JIT_REG_FLOAT32)
+#define JIT_REG_ARM_FLOAT64 (JIT_REG_FLOAT64 | JIT_REG_NFLOAT)
+
+#define JIT_REG_INFO_FLOAT_REGS \
+ {"s0", 0, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s1", 1, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s2", 2, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s3", 3, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s4", 4, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s5", 5, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s6", 6, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s7", 7, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s8", 8, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s9", 9, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s10", 10, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s11", 11, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s12", 12, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s13", 13, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s14", 14, -1, JIT_REG_ARM_FLOAT32}, \
+ {"s15", 15, -1, JIT_REG_ARM_FLOAT32}, \
+ {"d8", 8, -1, JIT_REG_ARM_FLOAT64}, \
+ {"d9", 9, -1, JIT_REG_ARM_FLOAT64}, \
+ {"d10", 10, -1, JIT_REG_ARM_FLOAT64}, \
+ {"d11", 11, -1, JIT_REG_ARM_FLOAT64}, \
+ {"d12", 12, -1, JIT_REG_ARM_FLOAT64}, \
+ {"d13", 13, -1, JIT_REG_ARM_FLOAT64}, \
+ {"d14", 14, -1, JIT_REG_ARM_FLOAT64}, \
+ {"d15", 15, -1, JIT_REG_ARM_FLOAT64},
+
+/* JIT_NUM_REGS is the total number of registers (general purpose+floating
point) */
+#define JIT_NUM_REGS 40
+
+#endif
+
+/* The number of global registers */
#define JIT_NUM_GLOBAL_REGS 3
+//Floating point registers are NOT handled like a stack
+#undef JIT_REG_STACK
+
/*
* Define to 1 if we should always load values into registers
* before operating on them. i.e. the CPU does not have reg-mem
@@ -90,7 +167,7 @@
/*
* Preferred alignment for the start of functions.
*/
-#define JIT_FUNCTION_ALIGNMENT 4
+#define JIT_FUNCTION_ALIGNMENT 8
/*
* Define this to 1 if the platform allows reads and writes on
@@ -103,23 +180,26 @@
* Extra state information that is added to the "jit_gencode" structure.
*/
#define JIT_ARM_MAX_CONSTANTS 32
+
#define jit_extra_gen_state \
int constants[JIT_ARM_MAX_CONSTANTS]; \
int *fixup_constants[JIT_ARM_MAX_CONSTANTS]; \
int num_constants; \
int align_constants; \
unsigned int *first_constant_use
+
#define jit_extra_gen_init(gen) \
do { \
(gen)->num_constants = 0; \
(gen)->align_constants = 0; \
(gen)->first_constant_use = 0; \
} while (0)
+
#define jit_extra_gen_cleanup(gen) do { ; } while (0)
/*
* Parameter passing rules. We start by assuming that lr, sp, fp,
- r8, r7, r6, r5, and r4 need to be saved in the local frame.
+ * r8, r7, r6, r5, and r4 need to be saved in the local frame.
*/
#define JIT_CDECL_WORD_REG_PARAMS {0, 1, 2, 3, -1}
#define JIT_MAX_WORD_REG_PARAMS 4
Index: jit/jit-rules-arm.c
===================================================================
RCS file: /sources/dotgnu-pnet/libjit/jit/jit-rules-arm.c,v
retrieving revision 1.24
retrieving revision 1.25
diff -u -b -r1.24 -r1.25
--- jit/jit-rules-arm.c 24 Jan 2008 20:12:53 -0000 1.24
+++ jit/jit-rules-arm.c 23 Mar 2009 13:14:22 -0000 1.25
@@ -2,6 +2,7 @@
* jit-rules-arm.c - Rules that define the characteristics of the ARM.
*
* Copyright (C) 2004 Southern Storm Software, Pty Ltd.
+ * Copyright (C) 2008 Michele Tartara <address@hidden>
*
* This file is part of the libjit library.
*
@@ -32,40 +33,216 @@
#include <stdio.h>
/*
+ * Pseudo register numbers for the ARM registers. These are not the
+ * same as the CPU instruction register numbers. The order of these
+ * values must match the order in "JIT_REG_INFO".
+ */
+#define ARM_REG_R0 0
+#define ARM_REG_R1 1
+#define ARM_REG_R2 2
+#define ARM_REG_R3 3
+#define ARM_REG_R4 4
+#define ARM_REG_R5 5
+#define ARM_REG_R6 6
+#define ARM_REG_R7 7
+#define ARM_REG_R8 8
+#define ARM_REG_R9 9
+#define ARM_REG_R10 10
+#define ARM_REG_FP 11
+#define ARM_REG_R12 12
+#define ARM_REG_SP 13
+#define ARM_REG_LR 14
+#define ARM_REG_PC 15
+
+#ifdef JIT_ARM_HAS_FPA
+#define ARM_F0 16
+#define ARM_F1 17
+#define ARM_F2 18
+#define ARM_F3 19
+#define ARM_F4 20
+#define ARM_F5 21
+#define ARM_F6 22
+#define ARM_F7 23
+#endif
+
+#ifdef JIT_ARM_HAS_VFP
+#define ARM_REG_S0 16
+#define ARM_REG_S1 17
+#define ARM_REG_S2 18
+#define ARM_REG_S3 19
+#define ARM_REG_S4 20
+#define ARM_REG_S5 21
+#define ARM_REG_S6 22
+#define ARM_REG_S7 23
+#define ARM_REG_S8 24
+#define ARM_REG_S9 25
+#define ARM_REG_S10 26
+#define ARM_REG_S11 27
+#define ARM_REG_S12 28
+#define ARM_REG_S13 29
+#define ARM_REG_S14 30
+#define ARM_REG_S15 31
+#define ARM_REG_D8 32
+#define ARM_REG_D9 33
+#define ARM_REG_D10 34
+#define ARM_REG_D11 35
+#define ARM_REG_D12 36
+#define ARM_REG_D13 37
+#define ARM_REG_D14 38
+#define ARM_REG_D15 39
+#endif
+
+/*
+ * Determine if a pseudo register number is word-based or float-based.
+ */
+#define IS_WORD_REG(reg) ((reg) <= ARM_REG_PC)
+#define IS_FLOAT_REG(reg) ((reg) > ARM_REG_PC)
+
+/*
* Round a size up to a multiple of the stack word size.
*/
#define ROUND_STACK(size) \
(((size) + (sizeof(void *) - 1)) & ~(sizeof(void *) - 1))
/*
+ * Define the classes of registers
+ */
+static _jit_regclass_t *arm_reg;
+static _jit_regclass_t *arm_freg;
+static _jit_regclass_t *arm_freg32;
+static _jit_regclass_t *arm_freg64;
+static _jit_regclass_t *arm_lreg;
+static _jit_regclass_t *arm_breg;
+
+/*
+ * -------------------- Helper functions --------------------------
+ */
+
+/**
* Load the instruction pointer from the generation context.
*/
#define jit_gen_load_inst_ptr(gen,inst) \
do { \
arm_inst_buf_init((inst), (gen)->posn.ptr,
(gen)->posn.limit); \
- } while (0)
+} while (0)
-/*
+/**
* Save the instruction pointer back to the generation context.
*/
#define jit_gen_save_inst_ptr(gen,inst) \
do { \
(gen)->posn.ptr = (unsigned char
*)arm_inst_get_posn(inst); \
- } while (0)
+} while (0)
-void _jit_init_backend(void)
-{
- /* Nothing to do here */
+/*
+* Get a temporary register that isn't one of the specified registers.
+* When this function is used EVERY REGISTER COULD BE DESTROYED!!!
+* TODO: this function is only used by JIT_OP_STORE_RELATIVE_STRUCT, through
memory_copy: remove
+* the need of using it by sustituting it with register allocation with
[scratch reg]
+*/
+static int get_temp_reg(int reg1, int reg2, int reg3)
+{
+ /*
+ * R0-R3 are not used because they could be needed for parameter
passing.
+ * R4 is not used because it's used by jit_apply to store the base of
the frame where
+ * it saves all the data it needs in order to restart execution after
calling a compiled function.
+ * R9 is not used because it's the platform register and could have
special
+ * uses on some ARM platform
+ * R11, R13-R15 are not used because they have special meaning on the
ARM platform.
+ * The other registers are candidates for
+ */
+ if(reg1 != ARM_R5 && reg2 != ARM_R5 && reg3 != ARM_R5)
+ {
+ return ARM_R5;
+ }
+ if(reg1 != ARM_R6 && reg2 != ARM_R6 && reg3 != ARM_R6)
+ {
+ return ARM_R6;
+ }
+ if(reg1 != ARM_R7 && reg2 != ARM_R7 && reg3 != ARM_R7)
+ {
+ return ARM_R7;
+ }
+ if(reg1 != ARM_R8 && reg2 != ARM_R8 && reg3 != ARM_R8)
+ {
+ return ARM_R8;
+ }
+ if(reg1 != ARM_R10 && reg2 != ARM_R10 && reg3 != ARM_R10)
+ {
+ return ARM_R10;
+ }
+ return ARM_R12;
}
-void _jit_gen_get_elf_info(jit_elf_info_t *info)
-{
- info->machine = 40; /* EM_ARM */
- info->abi = 0; /* ELFOSABI_SYSV */
- info->abi_version = 0;
-}
+static void mov_reg_imm (jit_gencode_t gen, arm_inst_buf *inst, int reg, int
value);
/*
+* Copy a block of memory that has a specific size. Other than
+* the parameter pointers, all registers must be unused at this point.
+*/
+static arm_inst_buf memory_copy (jit_gencode_t gen, arm_inst_buf inst, int
dreg, jit_nint doffset, int sreg, jit_nint soffset, jit_nuint size, int
temp_reg)
+{
+ //int temp_reg = get_temp_reg(dreg, sreg, -1);
+ if (temp_reg==-1) temp_reg = get_temp_reg(dreg, sreg, -1);
+ if(size <= 4 * sizeof(void *))
+ {
+ /* Use direct copies to copy the memory */
+ int offset = 0;
+ while(size >= sizeof(void *))
+ {
+ arm_mov_reg_membase(inst, temp_reg, sreg, soffset +
offset, sizeof(void *));
+ arm_mov_membase_reg(inst, dreg, doffset + offset,
temp_reg, sizeof(void *));
+ size -= sizeof(void *);
+ offset += sizeof(void *);
+ }
+ if(size >= 2)
+ {
+ arm_mov_reg_membase(inst, temp_reg, sreg, soffset +
offset, 2);
+ arm_mov_membase_reg(inst, dreg, doffset + offset,
temp_reg, 2);
+ size -= 2;
+ offset += 2;
+ }
+ if(size >= 1)
+ {
+ arm_mov_reg_membase(inst, temp_reg, sreg, soffset +
offset, 1);
+ arm_mov_membase_reg(inst, dreg, doffset + offset,
temp_reg, 1);
+ }
+ }
+ else
+ {
+ /* Call out to "jit_memcpy" to effect the copy */
+ //Load the parameters in the right registers
+ //R2 <- size
+ mov_reg_imm(gen, &inst, ARM_R2, size);
+ //R1 <- source pointer
+ if(soffset == 0)
+ {
+ arm_mov_reg_reg(inst, ARM_R1, sreg);
+ }
+ else
+ {
+ arm_alu_reg_imm(inst, ARM_ADD, temp_reg, sreg, soffset);
+ arm_mov_reg_reg(inst, ARM_R1, temp_reg);
+ }
+ //R0 <- destination pointer
+ /* On ARM, the stack doesn't need special treatment, since
parameters are passed using registers, not using the stack as it's done on x86
*/
+
+ if(doffset == 0)
+ {
+ arm_mov_reg_reg(inst, ARM_R0, dreg);
+ }
+ else
+ {
+ arm_alu_reg_imm(inst, ARM_ADD, temp_reg, dreg, doffset);
+ arm_mov_reg_reg(inst, ARM_R0, temp_reg);
+ }
+
+ arm_call(inst, jit_memcpy);
+ }
+ return inst;
+}
+
+/**
* Flush the contents of the constant pool.
*/
static void flush_constants(jit_gencode_t gen, int after_epilog)
@@ -126,7 +303,7 @@
}
if(value)
{
- fixup -= value;
+ fixup -= value / sizeof(void *);
}
else
{
@@ -148,7 +325,7 @@
jit_gen_save_inst_ptr(gen, inst);
}
-/*
+/**
* Perform a constant pool flush if we are too far from the starting point.
*/
static int flush_if_too_far(jit_gencode_t gen)
@@ -182,7 +359,7 @@
prev = gen->fixup_constants[index];
if(prev)
{
- value = fixup - prev;
+ value = (fixup - prev) * sizeof(void *);
}
else
{
@@ -190,10 +367,12 @@
}
if((*fixup & 0x0F000000) == 0x05000000)
{
+ //Word fixup
*fixup = ((*fixup & ~0x0FFF) | value);
}
else
{
+ //Float fixup
*fixup = ((*fixup & ~0x00FF) | (value / 4));
}
gen->fixup_constants[index] = fixup;
@@ -235,7 +414,7 @@
}
/*
- * Add a double-word immedite value to the constant pool.
+ * Add a double-word immediate value to the constant pool.
*/
static void add_constant_dword
(jit_gencode_t gen, int value1, int value2, arm_inst_word *fixup, int
align)
@@ -279,8 +458,8 @@
/* Add the double word constant value to the pool */
gen->constants[gen->num_constants] = value1;
gen->fixup_constants[gen->num_constants] = 0;
- gen->constants[gen->num_constants] = value2;
- gen->fixup_constants[gen->num_constants] = 0;
+ gen->constants[gen->num_constants+1] = value2;
+ gen->fixup_constants[gen->num_constants+1] = 0;
gen->num_constants += 2;
add_constant_fixup(gen, gen->num_constants - 2, fixup);
}
@@ -349,6 +528,201 @@
jit_gen_load_inst_ptr(gen, *inst);
}
+/*
+ * Output a branch instruction.
+ */
+static void output_branch
+ (jit_function_t func, arm_inst_buf *inst, int cond, jit_insn_t
insn)
+{
+ jit_block_t block;
+ int offset;
+ //block = jit_block_from_label(func, (jit_label_t)(insn->dest));
+ if((insn->flags & JIT_INSN_VALUE1_IS_LABEL) != 0)
+ {
+ /* "address_of_label" instruction */
+ block = jit_block_from_label(func, (jit_label_t)(insn->value1));
+ }
+ else
+ {
+ block = jit_block_from_label(func, (jit_label_t)(insn->dest));
+ }
+ if(!block)
+ {
+ return;
+ }
+ if(arm_inst_get_posn(*inst) >= arm_inst_get_limit(*inst))
+ {
+ /* The buffer has overflowed, so don't worry about fixups */
+ return;
+ }
+ if(block->address)
+ {
+ /* We already know the address of the block */
+ arm_branch(*inst, cond, block->address);
+ }
+ else
+ {
+ /* Output a placeholder and record on the block's fixup list */
+ if(block->fixup_list)
+ {
+ offset = (int)(((unsigned char
*)arm_inst_get_posn(*inst)) -
+ ((unsigned char *)(block->fixup_list)));
+ }
+ else
+ {
+ offset = 0;
+ }
+ arm_branch_imm(*inst, cond, offset);
+ block->fixup_list = (void *)(arm_inst_get_posn(*inst) - 1);
+ }
+}
+
+/*
+ * Throw a builtin exception.
+ */
+static void throw_builtin
+ (arm_inst_buf *inst, jit_function_t func, int cond, int type)
+{
+ arm_inst_word *patch;
+
+ /* Branch past the following code if "cond" is not true */
+ patch = arm_inst_get_posn(*inst);
+ arm_branch_imm(*inst, cond ^ 0x01, 0);
+
+ /* We need to update "catch_pc" if we have a "try" block */
+ if(func->builder->setjmp_value != 0)
+ {
+ _jit_gen_fix_value(func->builder->setjmp_value);
+ arm_mov_reg_reg(*inst, ARM_WORK, ARM_PC);
+ arm_store_membase(*inst, ARM_WORK, ARM_FP,
+ func->builder->setjmp_value->frame_offset +
+ jit_jmp_catch_pc_offset);
+ }
+
+ /* Push the exception type onto the stack */
+ arm_mov_reg_imm(*inst, ARM_WORK, type);
+ arm_push_reg(*inst, ARM_WORK);
+
+ /* Call the "jit_exception_builtin" function, which will never return */
+ arm_call(*inst, jit_exception_builtin);
+
+ /* Back-patch the previous branch instruction */
+ arm_patch(*inst, patch, arm_inst_get_posn(*inst));
+}
+
+/*
+ * Jump to the current function's epilog.
+ */
+static void jump_to_epilog
+ (jit_gencode_t gen, arm_inst_buf *inst, jit_block_t block)
+{
+ int offset;
+
+ /* If the epilog is the next thing that we will output,
+ then fall through to the epilog directly */
+ block = block->next;
+ while(block != 0 && block->first_insn > block->last_insn)
+ {
+ block = block->next;
+ }
+ if(!block)
+ {
+ return;
+ }
+
+ /* Bail out if the instruction buffer has overflowed */
+ if(arm_inst_get_posn(*inst) >= arm_inst_get_limit(*inst))
+ {
+ return;
+ }
+
+ /* Output a placeholder for the jump and add it to the fixup list */
+ if(gen->epilog_fixup)
+ {
+ offset = (int)(((unsigned char *)arm_inst_get_posn(*inst)) -
+ ((unsigned char *)(gen->epilog_fixup)));
+ }
+ else
+ {
+ offset = 0;
+ }
+ arm_branch_imm(*inst, ARM_CC_AL, offset);
+ gen->epilog_fixup = (void *)(arm_inst_get_posn(*inst) - 1);
+}
+
+#define TODO() \
+ do { \
+ fprintf(stderr, "TODO at %s, %d\n", __FILE__, (int)__LINE__); \
+} while (0)
+
+/*
+ * -------------------- End of helper functions ------------------------
+ */
+
+
+/**
+ * Initialize the backend.
+ */
+void _jit_init_backend(void)
+{
+ /*
+ * Init the various classes of registers
+ */
+
+ /* WORD registers */
+ arm_reg = _jit_regclass_create(
+ "reg", JIT_REG_WORD, 9,
+ ARM_REG_R0, ARM_REG_R1,
+ ARM_REG_R2, ARM_REG_R3,
+ ARM_REG_R4, ARM_REG_R5,
+ ARM_REG_R6, ARM_REG_R7,
+ ARM_REG_R8);
+
+#ifdef JIT_ARM_HAS_FPA
+ /* float registers */
+ arm_freg = _jit_regclass_create(
+ "freg64", JIT_REG_ARM_FLOAT, 4,
+ ARM_REG_F0, ARM_REG_F1,
+ ARM_REG_F2, ARM_REG_F3,
+ /*ARM_REG_F4, ARM_REG_F5,
+ ARM_REG_F6, ARM_REG_F7*/);
+#endif
+
+#ifdef JIT_ARM_HAS_VFP
+ /* 32-bits float registers */
+ arm_freg32 = _jit_regclass_create(
+ "freg32", JIT_REG_ARM_FLOAT32, 16,
+ ARM_REG_S0, ARM_REG_S1,
+ ARM_REG_S2, ARM_REG_S3,
+ ARM_REG_S4, ARM_REG_S5,
+ ARM_REG_S6, ARM_REG_S7,
+ ARM_REG_S8, ARM_REG_S9,
+ ARM_REG_S10, ARM_REG_S11,
+ ARM_REG_S12, ARM_REG_S13,
+ ARM_REG_S14, ARM_REG_S15);
+
+ /* 64-bits float registers */
+ arm_freg64 = _jit_regclass_create(
+ "freg64", JIT_REG_ARM_FLOAT64, 8,
+ ARM_REG_D8, ARM_REG_D9,
+ ARM_REG_D10, ARM_REG_D11,
+ ARM_REG_D12, ARM_REG_D13,
+ ARM_REG_D14, ARM_REG_D15);
+#endif
+
+ /* Long registers */
+ arm_lreg = _jit_regclass_create(
+ "lreg", JIT_REG_LONG, 2,
+ ARM_REG_R0, ARM_REG_R2);
+}
+
+void _jit_gen_get_elf_info(jit_elf_info_t *info)
+{
+ info->machine = 40; /* EM_ARM */
+ info->abi = 0; /* ELFOSABI_SYSV */
+ info->abi_version = 0;
+}
+
int _jit_setup_indirect_pointer(jit_function_t func, jit_value_t value)
{
return jit_insn_outgoing_reg(func, value, ARM_WORK);
@@ -367,7 +741,7 @@
ptr_return = jit_type_return_via_pointer(return_type);
if(!return_value || ptr_return)
{
- return 0;
+ return 1;
}
/* Structure values must be flushed into the frame, and
@@ -380,11 +754,18 @@
}
}
#ifdef JIT_ARM_HAS_FLOAT_REGS
- else if(return_type->kind == JIT_TYPE_FLOAT32 ||
- return_type->kind == JIT_TYPE_FLOAT64 ||
+ //TODO: check that this works when the handling of the float registers
changes
+ else if(return_type->kind == JIT_TYPE_FLOAT32)
+ {
+ if(!jit_insn_return_reg(func, return_value, ARM_REG_S0))
+ {
+ return 0;
+ }
+ }
+ else if(return_type->kind == JIT_TYPE_FLOAT64 ||
return_type->kind == JIT_TYPE_NFLOAT)
{
- if(!jit_insn_return_reg(func, return_value, 16 /* f0 */))
+ if(!jit_insn_return_reg(func, return_value, ARM_REG_D8))
{
return 0;
}
@@ -392,7 +773,7 @@
#endif
else if(return_type->kind != JIT_TYPE_VOID)
{
- if(!jit_insn_return_reg(func, return_value, 0 /* r0 */))
+ if(!jit_insn_return_reg(func, return_value, ARM_REG_R0))
{
return 0;
}
@@ -407,7 +788,7 @@
switch(opcode)
{
#define JIT_INCLUDE_SUPPORTED
- #include "jit-rules-arm.slc"
+ #include "jit-rules-arm.inc"
#undef JIT_INCLUDE_SUPPORTED
}
return 0;
@@ -420,6 +801,7 @@
int reg, regset;
unsigned int saved;
unsigned int frame_size;
+ unsigned int stack_growth;
/* Initialize the instruction buffer */
arm_inst_buf_init(inst, prolog, prolog + JIT_PROLOG_SIZE / sizeof(int));
@@ -443,8 +825,26 @@
/* Allocate space for the local variable frame. Subtract off
the space for the registers that we just saved. The pc, lr,
and fp registers are always saved, so account for them too */
+ stack_growth=(saved + 4 * sizeof(void *));
+ frame_size = func->builder->frame_size - stack_growth;
frame_size = func->builder->frame_size - (saved + 3 * sizeof(void *));
frame_size += (unsigned int)(func->builder->param_area_size);
+ while(frame_size % JIT_SP_ALIGN_PUBLIC != 0)
+ {
+ //Pad to reach the required stacl pointer alignment
+ frame_size++;
+ }
+
+ /* If the registers that get saved on the stack make it grow of a odd
number
+ * of words, the preceding while isn't able anymore to compute the
correct
+ * allignment. The following adds a correction when needed.
+ */
+ if (stack_growth % JIT_SP_ALIGN_PUBLIC != 0)
+ {
+ //Pad to reach the required stack pointer alignment
+ frame_size += (stack_growth % JIT_SP_ALIGN_PUBLIC);
+ }
+
if(frame_size > 0)
{
arm_alu_reg_imm(inst, ARM_SUB, ARM_SP, ARM_SP, frame_size);
@@ -504,6 +904,11 @@
flush_constants(gen, 1);
}
+#if 0
+/*
+ * The ARM backend does not need this function because it uses
+ * _jit_create_indirector() instead.
+ */
void *_jit_gen_redirector(jit_gencode_t gen, jit_function_t func)
{
void *ptr, *entry;
@@ -517,7 +922,7 @@
jit_gen_save_inst_ptr(gen, inst);
return entry;
}
-
+#endif
/*
* Setup or teardown the ARM code output process.
*/
@@ -527,6 +932,12 @@
#define jit_cache_end_output() \
jit_gen_save_inst_ptr(gen, inst)
+/**
+ * Spill the content of register "reg" (and "other_reg", if it's different
from -1)
+ * into the global register or the memory area associated with "value"
+ * NB: it doesn't set value->in_global_register or value->in_frame. The caller
has to
+ * take care of that.
+ */
void _jit_gen_spill_reg(jit_gencode_t gen, int reg,
int other_reg, jit_value_t
value)
{
@@ -542,14 +953,21 @@
/* Output an appropriate instruction to spill the value */
if(value->has_global_register)
{
- arm_mov_reg_reg(inst, _jit_reg_info[value->global_reg].cpu_reg,
- _jit_reg_info[reg].cpu_reg);
+ if (IS_FLOAT_REG(reg))
+ {
+ printf("TODO:Copy from float reg to global reg is not
handled properly in %s\n", __FILE__);
+ abort();
+ }
+ else
+ {
+ arm_mov_reg_reg(inst,
_jit_reg_info[value->global_reg].cpu_reg, _jit_reg_info[reg].cpu_reg);
+ }
}
else
{
_jit_gen_fix_value(value);
offset = (int)(value->frame_offset);
- if(reg < 16)
+ if(IS_WORD_REG(reg))
{
arm_store_membase(inst, reg, ARM_FP, offset);
if(other_reg != -1)
@@ -561,11 +979,11 @@
}
else if(jit_type_normalize(value->type)->kind ==
JIT_TYPE_FLOAT32)
{
- arm_store_membase_float32(inst, reg - 16, ARM_FP,
offset);
+ arm_store_membase_float32(inst,
_jit_reg_info[value->reg].cpu_reg, ARM_FP, offset);
}
else
{
- arm_store_membase_float64(inst, reg - 16, ARM_FP,
offset);
+ arm_store_membase_float64(inst,
_jit_reg_info[value->reg].cpu_reg, ARM_FP, offset);
}
}
@@ -624,7 +1042,7 @@
{
jit_float32 float32_value;
float32_value =
jit_value_get_float32_constant(value);
- if(reg < 16)
+ if(IS_WORD_REG(reg))
{
mov_reg_imm(gen, &inst,
_jit_reg_info[reg].cpu_reg,
*((int
*)&float32_value));
@@ -643,7 +1061,7 @@
{
jit_float64 float64_value;
float64_value =
jit_value_get_float64_constant(value);
- if(reg < 16)
+ if(IS_WORD_REG(reg))
{
mov_reg_imm
(gen, &inst,
_jit_reg_info[reg].cpu_reg,
@@ -665,6 +1083,26 @@
}
else if(value->has_global_register)
{
+ /*
+ * This value has been assinged a global register. This means
+ * that it can use that register, but not necessarily that it's
+ * already in it!!
+ */
+
+ /* Ensure that the value is already in the global_register */
+ if (!value->in_global_register)
+ {
+ /* Find the other register in a long pair */
+ int reg=value->reg;
+ int other_reg;
+ get_reg_and_other_reg(gen, ®, &other_reg);
+ //Spill to the global register
+ _jit_gen_spill_reg(gen, reg, other_reg, value);
+ value->in_global_register=1;
+
+ /* A new instruction has probably been generated by
_jit_gen_spill_reg: reload the inst pointer */
+ jit_gen_load_inst_ptr(gen, inst);
+ }
/* Load the value out of a global register */
arm_mov_reg_reg(inst, _jit_reg_info[reg].cpu_reg,
_jit_reg_info[value->global_reg].cpu_reg);
@@ -675,7 +1113,20 @@
_jit_gen_fix_value(value);
offset = (int)(value->frame_offset);
- /* Load the value into the specified register */
+ /* Ensure that the value is already in the stack frame */
+ if(value->in_register)
+ {
+ /* Find the other register in a long pair */
+ int reg=value->reg;
+ int other_reg;
+ get_reg_and_other_reg(gen, ®, &other_reg);
+ _jit_gen_spill_reg(gen, reg, other_reg, value);
+ value->in_frame=1;
+
+ /* A new instruction has probably been generated by
_jit_gen_spill_reg: reload the inst pointer */
+ jit_gen_load_inst_ptr(gen, inst);
+ }
+
switch(jit_type_normalize(value->type)->kind)
{
case JIT_TYPE_SBYTE:
@@ -726,7 +1177,7 @@
case JIT_TYPE_FLOAT32:
{
- if(reg < 16)
+ if(IS_WORD_REG(reg))
{
arm_load_membase(inst,
_jit_reg_info[reg].cpu_reg,
ARM_FP, offset);
@@ -742,7 +1193,7 @@
case JIT_TYPE_FLOAT64:
case JIT_TYPE_NFLOAT:
{
- if(reg < 16)
+ if(IS_WORD_REG(reg))
{
arm_load_membase(inst,
_jit_reg_info[reg].cpu_reg,
ARM_FP, offset);
@@ -763,160 +1214,110 @@
jit_cache_end_output();
}
-void _jit_gen_spill_global(jit_gencode_t gen, int reg, jit_value_t value)
+/**
+ * Loads a struct indicated by "value" into the given register reg
+ */
+void _jit_gen_load_value_struct (jit_gencode_t gen, int reg, jit_value_t value)
{
- /* TODO: Implement if ARM needs it. */
-}
+ int offset;
-void _jit_gen_load_global(jit_gencode_t gen, int reg, jit_value_t value)
-{
+ /* Make sure that we have sufficient space */
jit_cache_setup_output(32);
- arm_load_membase(inst, _jit_reg_info[value->global_reg].cpu_reg,
- ARM_FP, value->frame_offset);
- jit_cache_end_output();
-}
-
-void _jit_gen_exch_top(jit_gencode_t gen, int reg)
-{
-}
-
-void _jit_gen_move_top(jit_gencode_t gen, int reg)
-{
-}
-
-void _jit_gen_spill_top(jit_gencode_t gen, int reg, jit_value_t value, int pop)
-{
-}
-
-void _jit_gen_fix_value(jit_value_t value)
-{
- if(!(value->has_frame_offset) && !(value->is_constant))
+ if(flush_if_too_far(gen))
{
- jit_nint size =
(jit_nint)(ROUND_STACK(jit_type_get_size(value->type)));
- value->block->func->builder->frame_size += size;
- value->frame_offset =
-(value->block->func->builder->frame_size);
- value->has_frame_offset = 1;
+ jit_gen_load_inst_ptr(gen, inst);
}
-}
-/*
- * Output a branch instruction.
- */
-static void output_branch
- (jit_function_t func, arm_inst_buf *inst, int cond, jit_insn_t insn)
-{
- jit_block_t block;
- int offset;
- block = jit_block_from_label(func, (jit_label_t)(insn->dest));
- if(!block)
+ if(value->is_constant)
{
- return;
+ TODO();
+ abort();
}
- if(arm_inst_get_posn(*inst) >= arm_inst_get_limit(*inst))
+ else if(value->has_global_register)
{
- /* The buffer has overflowed, so don't worry about fixups */
- return;
- }
- if(block->address)
+ /*
+ * This value has been assinged a global register. This means
+ * that it can use that register, but not necessarily that it's
+ * already in it!!
+ */
+
+ /* Ensure that the value is already in the global_register */
+ if (!value->in_global_register)
{
- /* We already know the address of the block */
- arm_branch(*inst, cond, block->address);
+ /* Find the other register in a long pair */
+ int reg=value->reg;
+ int other_reg;
+ get_reg_and_other_reg(gen, ®, &other_reg);
+ //Spill to the global register
+ _jit_gen_spill_reg(gen, reg, other_reg, value);
+ value->in_global_register=1;
+
+ /* A new instruction has probably been generated by
_jit_gen_spill_reg: reload the inst pointer */
+ jit_gen_load_inst_ptr(gen, inst);
}
- else
- {
- /* Output a placeholder and record on the block's fixup list */
- if(block->fixup_list)
- {
- offset = (int)(((unsigned char
*)arm_inst_get_posn(*inst)) -
- ((unsigned char
*)(block->fixup_list)));
+ /* Load the value out of a global register */
+ arm_mov_reg_reg(inst, _jit_reg_info[reg].cpu_reg,
+
_jit_reg_info[value->global_reg].cpu_reg);
}
else
{
- offset = 0;
- }
- arm_branch_imm(*inst, cond, offset);
- block->fixup_list = (void *)(arm_inst_get_posn(*inst) - 1);
- }
-}
+ /* Fix the position of the value in the stack frame */
+ _jit_gen_fix_value(value);
+ offset = (int)(value->frame_offset);
-/*
- * Throw a builtin exception.
- */
-static void throw_builtin
- (arm_inst_buf *inst, jit_function_t func, int cond, int type)
-{
- arm_inst_word *patch;
+ /* Ensure that the value is already in the stack frame */
+ if(value->in_register)
+ {
+ /* Find the other register in a long pair */
+ int reg=value->reg;
+ int other_reg;
+ get_reg_and_other_reg(gen, ®, &other_reg);
+ _jit_gen_spill_reg(gen, reg, other_reg, value);
+ value->in_frame=1;
- /* Branch past the following code if "cond" is not true */
- patch = arm_inst_get_posn(*inst);
- arm_branch_imm(*inst, cond ^ 0x01, 0);
+ /* A new instruction has probably been generated by
_jit_gen_spill_reg: reload the inst pointer */
+ jit_gen_load_inst_ptr(gen, inst);
+ }
- /* We need to update "catch_pc" if we have a "try" block */
- if(func->builder->setjmp_value != 0)
+ assert(jit_type_normalize(value->type)->kind==JIT_TYPE_STRUCT);
+
+ arm_load_membase(inst, _jit_reg_info[reg].cpu_reg, ARM_FP,
offset);
+ if (jit_type_get_size(jit_value_get_type(value)) > 4)
{
- _jit_gen_fix_value(func->builder->setjmp_value);
- arm_mov_reg_reg(*inst, ARM_WORK, ARM_PC);
- arm_store_membase(*inst, ARM_WORK, ARM_FP,
-
func->builder->setjmp_value->frame_offset +
- jit_jmp_catch_pc_offset);
+ TODO();
+ abort();
}
- /* Push the exception type onto the stack */
- arm_mov_reg_imm(*inst, ARM_WORK, type);
- arm_push_reg(*inst, ARM_WORK);
-
- /* Call the "jit_exception_builtin" function, which will never return */
- arm_call(*inst, jit_exception_builtin);
+ }
- /* Back-patch the previous branch instruction */
- arm_patch(*inst, patch, arm_inst_get_posn(*inst));
+ /* End the code output process */
+ jit_cache_end_output();
}
-/*
- * Jump to the current function's epilog.
- */
-static void jump_to_epilog
- (jit_gencode_t gen, arm_inst_buf *inst, jit_block_t block)
+void _jit_gen_spill_global(jit_gencode_t gen, int reg, jit_value_t value)
{
- int offset;
-
- /* If the epilog is the next thing that we will output,
- then fall through to the epilog directly */
- block = block->next;
- while(block != 0 && block->first_insn > block->last_insn)
- {
- block = block->next;
- }
- if(!block)
- {
- return;
- }
+ /* TODO: Implement if ARM needs it. */
+}
- /* Bail out if the instruction buffer has overflowed */
- if(arm_inst_get_posn(*inst) >= arm_inst_get_limit(*inst))
- {
- return;
- }
+void _jit_gen_load_global(jit_gencode_t gen, int reg, jit_value_t value)
+{
+ jit_cache_setup_output(32);
+ arm_load_membase(inst, _jit_reg_info[value->global_reg].cpu_reg,
+ ARM_FP, value->frame_offset);
+ jit_cache_end_output();
+}
- /* Output a placeholder for the jump and add it to the fixup list */
- if(gen->epilog_fixup)
- {
- offset = (int)(((unsigned char *)arm_inst_get_posn(*inst)) -
- ((unsigned char
*)(gen->epilog_fixup)));
- }
- else
+void _jit_gen_fix_value(jit_value_t value)
+{
+ if(!(value->has_frame_offset) && !(value->is_constant))
{
- offset = 0;
+ jit_nint size =
(jit_nint)(ROUND_STACK(jit_type_get_size(value->type)));
+ value->block->func->builder->frame_size += size;
+ value->frame_offset =
-(value->block->func->builder->frame_size);
+ value->has_frame_offset = 1;
}
- arm_branch_imm(*inst, ARM_CC_AL, offset);
- gen->epilog_fixup = (void *)(arm_inst_get_posn(*inst) - 1);
}
-#define TODO() \
- do { \
- fprintf(stderr, "TODO at %s, %d\n", __FILE__, (int)__LINE__); \
- } while (0)
-
void _jit_gen_insn(jit_gencode_t gen, jit_function_t func,
jit_block_t block, jit_insn_t insn)
{
@@ -924,7 +1325,7 @@
switch(insn->opcode)
{
#define JIT_INCLUDE_RULES
- #include "jit-rules-arm.slc"
+ #include "jit-rules-arm.inc"
#undef JIT_INCLUDE_RULES
default:
@@ -985,4 +1386,29 @@
return 0;
}
+/** "value" is a float value (single or double) that has just been returned
+ * by a function and is in r0 (and, if needed, r1).
+ * If it is a float value, this function puts it back where it should be, in
the float register reg
+ * (of appropriate size)
+ */
+void _jit_gen_return_to_float(jit_gencode_t gen, jit_value_t value, int reg)
+{
+ if (IS_FLOAT_REG(reg))
+ {
+ arm_inst_buf inst;
+ jit_gen_load_inst_ptr(gen, inst);
+
+ if (value->type->kind == JIT_TYPE_FLOAT64
+ || value->type->kind == JIT_TYPE_NFLOAT)
+ {
+ arm_mov_double_reg_reg(inst,
_jit_reg_info[reg].cpu_reg, 0, 1);
+ }
+ else if (value->type->kind==JIT_TYPE_FLOAT32)
+ {
+ arm_mov_float_reg(inst, _jit_reg_info[reg].cpu_reg, 0);
+ }
+ jit_gen_save_inst_ptr(gen, inst);
+ }
+}
+
#endif /* JIT_BACKEND_ARM */
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [dotgnu-pnet-commits] libjit ChangeLog jit/jit-rules-arm.h jit/jit-ru...,
Aleksey Demakov <=