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[dotgnu-pnet-commits] libjit ChangeLog jit/jit-rules-arm.ins
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From: |
Aleksey Demakov |
|
Subject: |
[dotgnu-pnet-commits] libjit ChangeLog jit/jit-rules-arm.ins |
|
Date: |
Sun, 22 Mar 2009 21:33:27 +0000 |
CVSROOT: /sources/dotgnu-pnet
Module name: libjit
Changes by: Aleksey Demakov <avd> 09/03/22 21:33:27
Modified files:
. : ChangeLog
jit : jit-rules-arm.ins
Log message:
restore ARM FPA rules
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/libjit/ChangeLog?cvsroot=dotgnu-pnet&r1=1.409&r2=1.410
http://cvs.savannah.gnu.org/viewcvs/libjit/jit/jit-rules-arm.ins?cvsroot=dotgnu-pnet&r1=1.1&r2=1.2
Patches:
Index: ChangeLog
===================================================================
RCS file: /sources/dotgnu-pnet/libjit/ChangeLog,v
retrieving revision 1.409
retrieving revision 1.410
diff -u -b -r1.409 -r1.410
--- ChangeLog 22 Mar 2009 21:22:05 -0000 1.409
+++ ChangeLog 22 Mar 2009 21:33:27 -0000 1.410
@@ -2,6 +2,7 @@
* jit/jit-gen-arm.h: add more ARM codegen macros including VFP
support.
+ * jit/jit-rules-arm.ins: restore FPA rules.
2009-02-07 Aleksey Demakov <address@hidden>
Index: jit/jit-rules-arm.ins
===================================================================
RCS file: /sources/dotgnu-pnet/libjit/jit/jit-rules-arm.ins,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- jit/jit-rules-arm.ins 5 Feb 2009 21:21:07 -0000 1.1
+++ jit/jit-rules-arm.ins 22 Mar 2009 21:33:27 -0000 1.2
@@ -28,6 +28,7 @@
%regclass reg arm_reg
%regclass freg32 arm_freg32
%regclass freg64 arm_freg64
+%regclass freg arm_freg
%lregclass lreg arm_lreg
%regclass breg arm_breg
@@ -207,56 +208,106 @@
arm_alu_reg_imm8(inst, ARM_ADC, %1, %1, 0);
}
-JIT_OP_FADD (JIT_ARM_HAS_FLOAT_REGS):
+JIT_OP_FADD (JIT_ARM_HAS_VFP):
[freg32, freg32] -> {
arm_alu_freg_freg_32(inst, ARM_FADD, $1, $1, $2);
}
-JIT_OP_FSUB (JIT_ARM_HAS_FLOAT_REGS):
+JIT_OP_FADD (JIT_ARM_HAS_FPA): /*binary*/
+ [freg, freg] -> {
+ arm_alu_freg_freg_32(inst, ARM_ADF, $1, $1, $2);
+ }
+
+JIT_OP_FSUB (JIT_ARM_HAS_VFP):
[freg32, freg32] -> {
arm_alu_freg_freg_32(inst, ARM_FSUB, $1, $1, $2);
}
-JIT_OP_FMUL (JIT_ARM_HAS_FLOAT_REGS):
+JIT_OP_FSUB (JIT_ARM_HAS_FPA): /*binary*/
+ [freg, freg] -> {
+ arm_alu_freg_freg_32(inst, ARM_SUF, $1, $1, $2);
+ }
+
+JIT_OP_FMUL (JIT_ARM_HAS_VFP):
[freg32, freg32] -> {
arm_alu_freg_freg_32(inst, ARM_FMUL, $1, $1, $2);
}
-JIT_OP_FDIV (JIT_ARM_HAS_FLOAT_REGS):
+JIT_OP_FMUL (JIT_ARM_HAS_FPA): /*binary*/
+ [freg, freg] -> {
+ arm_alu_freg_freg_32(inst, ARM_MUF, $1, $1, $2);
+ }
+
+JIT_OP_FDIV (JIT_ARM_HAS_VFP):
[freg32, freg32] -> {
arm_alu_freg_freg_32(inst, ARM_FDIV, $1, $1, $2);
}
-JIT_OP_FNEG (JIT_ARM_HAS_FLOAT_REGS):
+JIT_OP_FDIV (JIT_ARM_HAS_FPA): /*binary*/
+ [freg, freg] -> {
+ arm_alu_freg_freg_32(inst, ARM_DVF, $1, $1, $2);
+ }
+
+JIT_OP_FNEG (JIT_ARM_HAS_VFP):
[freg32] -> {
arm_alu_freg_32(inst, ARM_MNF, $1, $1);
}
-JIT_OP_DADD, JIT_OP_NFADD (JIT_ARM_HAS_FLOAT_REGS):
+JIT_OP_FNEG (JIT_ARM_HAS_FPA): /*unary*/
+ [freg] -> {
+ arm_alu_freg_32(inst, ARM_MNF, $1, $1);
+ }
+
+JIT_OP_DADD, JIT_OP_NFADD (JIT_ARM_HAS_VFP):
[freg64, freg64] -> {
arm_alu_freg_freg(inst, ARM_FADD, $1, $1, $2);
}
-JIT_OP_DSUB, JIT_OP_NFSUB (JIT_ARM_HAS_FLOAT_REGS):
+JIT_OP_DADD, JIT_OP_NFADD (JIT_ARM_HAS_FPA): /*binary*/
+ [freg, freg] -> {
+ arm_alu_freg_freg(inst, ARM_ADF, $1, $1, $2);
+ }
+
+JIT_OP_DSUB, JIT_OP_NFSUB (JIT_ARM_HAS_VFP):
[freg64, freg64] -> {
arm_alu_freg_freg(inst, ARM_FSUB, $1, $1, $2);
}
-JIT_OP_DMUL, JIT_OP_NFMUL (JIT_ARM_HAS_FLOAT_REGS):
+JIT_OP_DSUB, JIT_OP_NFSUB (JIT_ARM_HAS_FPA): /*binary*/
+ [freg, freg] -> {
+ arm_alu_freg_freg(inst, ARM_SUF, $1, $1, $2);
+ }
+
+JIT_OP_DMUL, JIT_OP_NFMUL (JIT_ARM_HAS_VFP):
[freg64, freg64] -> {
arm_alu_freg_freg(inst, ARM_FMUL, $1, $1, $2);
}
-JIT_OP_DDIV, JIT_OP_NFDIV (JIT_ARM_HAS_FLOAT_REGS):
+JIT_OP_DMUL, JIT_OP_NFMUL (JIT_ARM_HAS_FPA): /*binary*/
+ [freg, freg] -> {
+ arm_alu_freg_freg(inst, ARM_MUF, $1, $1, $2);
+ }
+
+JIT_OP_DDIV, JIT_OP_NFDIV (JIT_ARM_HAS_VFP):
[freg64, freg64] -> {
arm_alu_freg_freg(inst, ARM_FDIV, $1, $1, $2);
}
-JIT_OP_DNEG, JIT_OP_NFNEG (JIT_ARM_HAS_FLOAT_REGS):
+JIT_OP_DDIV, JIT_OP_NFDIV (JIT_ARM_HAS_FPA): /*binary*/
+ [freg, freg] -> {
+ arm_alu_freg_freg(inst, ARM_DVF, $1, $1, $2);
+ }
+
+JIT_OP_DNEG, JIT_OP_NFNEG (JIT_ARM_HAS_VFP):
[freg64] -> {
arm_alu_freg(inst, ARM_MNF, $1, $1);
}
+JIT_OP_DNEG, JIT_OP_NFNEG (JIT_ARM_HAS_FPA): /*unary*/
+ [freg] -> {
+ arm_alu_freg(inst, ARM_MNF, $1, $1);
+ }
+
/*
* Bitwise opcodes.
*/
@@ -701,12 +752,22 @@
jump_to_epilog(gen, &inst, block);
}
-JIT_OP_RETURN_FLOAT32 (JIT_ARM_HAS_FLOAT_REGS): branch
+JIT_OP_RETURN_FLOAT32 (JIT_ARM_HAS_VFP): branch
[freg32, clobber("r0")] -> {
arm_mov_reg_float(inst, ARM_R0, $1);
jump_to_epilog(gen, &inst, block);
}
+JIT_OP_RETURN_FLOAT32 (JIT_ARM_HAS_FPA): branch
+ [freg] -> {
+ if($1 != 0)
+ {
+ arm_alu_freg_32(inst, ARM_MVF, ARM_F0, $1);
+ }
+ jump_to_epilog(gen, &inst, block);
+ }
+
+
JIT_OP_RETURN_FLOAT32 (!JIT_ARM_HAS_FLOAT_REGS): manual
[] -> {
arm_inst_buf inst;
@@ -727,12 +788,21 @@
}
JIT_OP_RETURN_FLOAT64, JIT_OP_RETURN_NFLOAT
- (JIT_ARM_HAS_FLOAT_REGS): branch
+ (JIT_ARM_HAS_VFP): branch
[freg64, clobber("r0", "r1")] -> {
arm_mov_reg_reg_double(inst,ARM_R0,ARM_R1, $1);
jump_to_epilog(gen, &inst, block);
}
+JIT_OP_RETURN_FLOAT64, JIT_OP_RETURN_NFLOAT (JIT_ARM_HAS_FPA): branch
+ [freg] -> {
+ if($1 != 0)
+ {
+ arm_alu_freg(inst, ARM_MVF, ARM_F0, $1);
+ }
+ jump_to_epilog(gen, &inst, block);
+ }
+
JIT_OP_RETURN_FLOAT64, JIT_OP_RETURN_NFLOAT (!JIT_ARM_HAS_FLOAT_REGS): manual
[] -> {
arm_inst_buf inst;
@@ -1430,12 +1500,12 @@
}
}
-JIT_OP_LOAD_RELATIVE_FLOAT32:
+JIT_OP_LOAD_RELATIVE_FLOAT32 (JIT_ARM_HAS_VFP):
[=freg32, reg, imm] -> {
arm_fld_membase(inst, $1, $2, $3, 0);
}
-JIT_OP_LOAD_RELATIVE_FLOAT64:
+JIT_OP_LOAD_RELATIVE_FLOAT64 (JIT_ARM_HAS_VFP):
[=freg64, reg, imm] -> {
arm_fld_membase(inst, $1, $2, $3, 1);
}
@@ -1510,7 +1580,7 @@
arm_mov_membase_reg(inst, $1, $3 + 4, %2, 4);
}
-JIT_OP_STORE_RELATIVE_FLOAT32: ternary
+JIT_OP_STORE_RELATIVE_FLOAT32 (JIT_ARM_HAS_VFP): ternary
[reg, imm, imm] -> {
arm_mov_membase_imm(inst, $1, $3, ((int *)($2))[0], 4,
ARM_WORK);
}
@@ -1518,7 +1588,7 @@
arm_store_membase_float32(inst, $2, $1, $3);
}
-JIT_OP_STORE_RELATIVE_FLOAT64: ternary
+JIT_OP_STORE_RELATIVE_FLOAT64 (JIT_ARM_HAS_VFP): ternary
[reg, imm, imm, scratch reg] -> {
arm_mov_membase_imm(inst, $1, $3, ((int *)($2))[0], 4, $4);
arm_mov_membase_imm(inst, $1, $3 + 4, ((int *)($2))[1], 4, $4);
@@ -1636,6 +1706,24 @@
arm_mov_memindex_reg(inst, $1, 0, $2, 2, $3, 4, $4);
}
+JIT_OP_STORE_ELEMENT_LONG: ternary
+ [reg, reg, imm] -> {
+ TODO();
+ abort();
+ //x86_mov_memindex_imm(inst, $1, 0, $2, 3, *(int *)($3), 4);
+ //x86_mov_memindex_imm(inst, $1, 4, $2, 3, *(int *)($3 + 4), 4);
+ }
+ [reg, reg, local, scratch reg, scratch reg] -> {
+ arm_mov_reg_membase(inst, $4, ARM_FP, $3, 4);
+ arm_mov_memindex_reg(inst, $1, 0, $2, 3, $4, 4, $5);
+ arm_mov_reg_membase(inst, $4, ARM_FP, $3 + 4, 4);
+ arm_mov_memindex_reg(inst, $1, 4, $2, 3, $4, 4, $5);
+ }
+ [reg, reg, lreg, scratch reg] -> {
+ arm_mov_memindex_reg(inst, $1, 0, $2, 3, $3, 4, $4);
+ arm_mov_memindex_reg(inst, $1, 4, $2, 3, %3, 4, $4);
+ }
+
JIT_OP_STORE_ELEMENT_FLOAT64: ternary
[reg, reg, freg64, scratch reg] -> {
arm_fst_memindex(inst, $3, $1, 0, $2, 3, 1, $4);
- [dotgnu-pnet-commits] libjit ChangeLog jit/jit-rules-arm.ins,
Aleksey Demakov <=