Encountered a problem importing Verilog

[Robert Mykland]

I am new to electric, so thought I would post this to the discussion 
group rather than the bug list, since I don't know yet whether or how 
much the behavior is a bug versus operator error.  Here's what I attempted:

1. Launched the electric-9.06.jar under Mac OS X Yosemite 10.10.5.
2. Selected "File->Import->Verilog..." from the menu.
3. Selected lut3to1_1.v in the resulting "Open File" menu (full listing 
below).
4. A system dialog box opened saying "Exception Caught!!! The exception 
below has been logged in '/Users/mykland/electric.log'. 
java.lang.NullPointerException.
5. Clicked the OK button in the dialog box.
6. In the "Electric Messages" window, received the following text:

Importing '/Users/mykland/work/chisel/lut3to1_1.v'
java.lang.NullPointerException
    at 
com.sun.electric.tool.user.CompileVerilogStruct$VModule.access$400(CompileVerilogStruct.java:87)
    at 
com.sun.electric.tool.user.CompileVerilogStruct.getSignalNames(CompileVerilogStruct.java:1687)
    at 
com.sun.electric.tool.user.CompileVerilogStruct.parseAssign(CompileVerilogStruct.java:1321)
    at 
com.sun.electric.tool.user.CompileVerilogStruct.doParser(CompileVerilogStruct.java:1040)
    at 
com.sun.electric.tool.user.CompileVerilogStruct.processVerilog(CompileVerilogStruct.java:359)
    at 
com.sun.electric.tool.user.CompileVerilogStruct.<init>(CompileVerilogStruct.java:291)
    at 
com.sun.electric.tool.io.input.verilog.VerilogReader$VerilogPreferences.doInput(VerilogReader.java:79)
    at com.sun.electric.tool.io.input.Input.importLibrary(Input.java:154)
    at 
com.sun.electric.tool.user.menus.FileMenu$ImportLibrary.doIt(FileMenu.java:765)
    at com.sun.electric.tool.EThread.run(EThread.java:92)

Full listing of lut3to1_1.v appears below:

module lut3to1_1(
    input [7:0] io_config,
    input  io_a,
    input  io_b,
    input  io_c,
    output io_out
);

  wire T0;
  wire T1;
  wire bc3;
  wire T2;
  wire T3;
  wire T4;
  wire T5;
  wire T6;
  wire T7;
  wire T8;
  wire T9;
  wire T10;
  wire bc2;
  wire T11;
  wire T12;
  wire T13;
  wire T14;
  wire T15;
  wire T16;
  wire T17;
  wire T18;
  wire T19;
  wire T20;
  wire bc1;
  wire T21;
  wire T22;
  wire T23;
  wire T24;
  wire T25;
  wire T26;
  wire T27;
  wire T28;
  wire T29;
  wire T30;
  wire bc0;
  wire T31;
  wire T32;
  wire T33;
  wire T34;
  wire T35;
  wire T36;
  wire T37;


  assign io_out = T0;
  assign T0 = T4 | T1;
  assign T1 = T2 & bc3;
  assign bc3 = io_b & io_c;
  assign T2 = T3 & io_a;
  assign T3 = io_config[3'h7:3'h7];
  assign T4 = T9 | T5;
  assign T5 = T6 & bc3;
  assign T6 = T8 & T7;
  assign T7 = ~ io_a;
  assign T8 = io_config[3'h6:3'h6];
  assign T9 = T14 | T10;
  assign T10 = T12 & bc2;
  assign bc2 = T11 & io_c;
  assign T11 = ~ io_b;
  assign T12 = T13 & io_a;
  assign T13 = io_config[3'h5:3'h5];
  assign T14 = T19 | T15;
  assign T15 = T16 & bc2;
  assign T16 = T18 & T17;
  assign T17 = ~ io_a;
  assign T18 = io_config[3'h4:3'h4];
  assign T19 = T24 | T20;
  assign T20 = T22 & bc1;
  assign bc1 = io_b & T21;
  assign T21 = ~ io_c;
  assign T22 = T23 & io_a;
  assign T23 = io_config[2'h3:2'h3];
  assign T24 = T29 | T25;
  assign T25 = T26 & bc1;
  assign T26 = T28 & T27;
  assign T27 = ~ io_a;
  assign T28 = io_config[2'h2:2'h2];
  assign T29 = T34 | T30;
  assign T30 = T32 & bc0;
  assign bc0 = ~ T31;
  assign T31 = io_b & io_c;
  assign T32 = T33 & io_a;
  assign T33 = io_config[1'h1:1'h1];
  assign T34 = T35 & bc0;
  assign T35 = T37 & T36;
  assign T36 = ~ io_a;
  assign T37 = io_config[1'h0:1'h0];
endmodule

-- Robert

--
Robert Mykland               Voice: (831) 212-0622
Founder/CTO                   Ascenium Corporation
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