my patch on busses

[Tuukka Toivonen]

A while ago I posted here a patch, without which electric generated broken
(uncompilable) vhdl code when busses were used hierarchially.

However, it seems that my patch may generate broken vhdl code that
compiles but for which simulator gives incorrect results. (Or maybe the
bug is elsewhere in electric, but since i cannot even compile the vhdl
without the patch, I can not know).

Here's example what can go wrong:

------
-- VHDL automatically generated from facet test{sch}
entity test is port(in1_0_, in1_1_, in1_2_, in1_3_, in2_0_, in2_1_,
 in2_2_, in2_3_, crin: in BIT; out_0_, out_1_, out_2_, out_3_, crout:
 out BIT);
  end test;
architecture test_BODY of test is
  component ADD4_CLA port(A_0_, A_1_, A_2_, A_3_, B_0_, B_1_, B_2_,
 B_3_, Cin: in BIT; S_0_, S_1_, S_2_, S_3_, Cout: out BIT);
    end component;
begin
  node6: ADD4_CLA port map(in2_0_, in2_1_, in2_2_, in2_3_, crin,
 in1_0_, in1_1_, in1_2_, in1_3_, out_0_, out_1_, out_2_, out_3_,
 crout);
end test_BODY;
------

The statement "port map" contains the ports in wrong order.

(this is 4-bit carry lookahead adder, crin,crout=carry in,out)

I'll look whats wrong (but others are free to do the same!)

This is for warning to anybody who's using the patch--though I know nobody
is anyway.