Re: busses on icons (simulation)

[Tuukka Toivonen]

On Thu, 14 Jun 2001, Tuukka Toivonen wrote:

> How can I get busses exported on a component icon?

My mistake. I thought it was export, it looked like an export, but it
wasn't really an export but just a bus name. I fixed the mistake and the
editor seems to be ok now, but I have now another problem.

I created a new schematic and inserted my bus-exporting component into
it. I connect wire to wire output, create export "out", connect bus to bus
input, create into it export "inp[0:7]" and try to run simulator, but it
says:
  Converting layout in facet tmp{sch}, writing VHDL to facet tmp{vhdl}
  ERROR on line 10, Instance has different number of ports that component:
  node3: A_NOR8 port map(inp_0_7_, outNV); 
                       ^
  ERRORS during compilation, no output produced

Looking at the generated VHDL, I see:

entity tmp is port(inp_0_, inp_1_, inp_2_, inp_3_, inp_4_, inp_5_,
 inp_6_, inp_7_: in BIT; outNV: out BIT);
  end tmp;
architecture tmp_BODY of tmp is
  component A_NOR8 port(a_0_, a_1_, a_2_, a_3_, a_4_, a_5_, a_6_,
 a_7_: in BIT; r: out BIT);
    end component;
begin
  node3: A_NOR8 port map(inp_0_7_, outNV);
end tmp_BODY;

-- VHDL automatically generated from facet A_NOR8{sch}
entity A_NOR8 is port(a_0_, a_1_, a_2_, a_3_, a_4_, a_5_, a_6_, a_7_:
 in BIT; r: out BIT);
  end A_NOR8;
architecture A_NOR8_BODY of A_NOR8 is
...

... i don't know very well VHDL, but there seems to be a problem with the
"A_NOR8 port map(inp_0_7_, outNV)" statement. If I replace "inp_0_7_"
with "inp_0_, inp_1_, "...", inp_7_", it works but that is too cumbersome
to do with hand every time. Any easy fix?