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From: | Steven Rubin |
Subject: | Re: flipflops vs. latches and busses and bugs |
Date: | Wed, 06 Jun 2001 07:59:55 -0700 |
Now I understand why Electric "flipflops" behaved strangely. The reason is that they are NOT flipflops at all but latches instead. Flipflop is edge triggered, latch is level triggered. This is the custom I see used in practically all places. Those items what are named "flipflops" are really latches. Fortunately it is easy to construct a real flipflop from two latches. But I do think that Electric is a small bug here.
Electric lets you choose the type of triggering for the "flipflops": positive, negative, or M/S. However, only one type of triggering is available in the simulation models. The bug may be that the wrong type of triggering is accepted by the simulator, and the others should be flagged as "unavailable for simulation".
What comes to the "busses don't work with the simulator", the bug might not be with busses actually. I got the same behaviour with wires. Also, to my surprise, I got the busses working at least in some situation. When I cut out the bus signals into separate wires, buffered them, and then assembled back to bus, it seems to work in the simulator. In the waveform display, I can set the value of the incoming bus to something and the signals going in the outgoing bus are updated accordingly, just as it should be. However, if I combine the signals of the outgoing bus into one (with the "B"-key), the waveform display seems to show a wrong value (althought it displays just the right value for incoming bus). The incoming bus is 2 signals wide. The outgoing should show same values, but instead I get the following: 0b00 -> 0b00 0b01 -> 0b01 0b10 -> 0b00 <- wrong 0b11 -> 0b11 0b10 -> 0b10 0b01 -> 0b00 <- wrong 0b11 -> 0b11 0b01 -> 0b01 The signals itself are correct, as I can see by double-clicking the outgoing bus, but sometimes the bus shows incorrectly "0". What's wrong? The same happens with all number bases.
When in doubt, look at the VHDL. Electric converts circuits to VHDL, then compiles them to netlists, and finally uses those netlists in simulation. If some of the circuit structure is being simulated strangely, look at the VHDL and it may become clear.
-Steven Rubin
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