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hurd-l4/libl4/ia32 Makefile.am l4/bits/ipc.h l4...
|
From: |
Marcus Brinkmann |
|
Subject: |
hurd-l4/libl4/ia32 Makefile.am l4/bits/ipc.h l4... |
|
Date: |
Mon, 22 Sep 2003 16:52:08 -0400 |
CVSROOT: /cvsroot/hurd
Module name: hurd-l4
Branch:
Changes by: Marcus Brinkmann <address@hidden> 03/09/22 16:52:07
Modified files:
libl4/ia32 : Makefile.am
libl4/ia32/l4/bits: ipc.h kip.h math.h misc.h space.h stubs.h
syscall.h types.h vregs.h
Log message:
Fix last change. Ouch!
CVSWeb URLs:
http://savannah.gnu.org/cgi-bin/viewcvs/hurd/hurd-l4/libl4/ia32/Makefile.am.diff?tr1=1.1&tr2=1.2&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/hurd/hurd-l4/libl4/ia32/l4/bits/ipc.h.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/hurd/hurd-l4/libl4/ia32/l4/bits/kip.h.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/hurd/hurd-l4/libl4/ia32/l4/bits/math.h.diff?tr1=1.4&tr2=1.5&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/hurd/hurd-l4/libl4/ia32/l4/bits/misc.h.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/hurd/hurd-l4/libl4/ia32/l4/bits/space.h.diff?tr1=1.3&tr2=1.4&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/hurd/hurd-l4/libl4/ia32/l4/bits/stubs.h.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/hurd/hurd-l4/libl4/ia32/l4/bits/syscall.h.diff?tr1=1.3&tr2=1.4&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/hurd/hurd-l4/libl4/ia32/l4/bits/types.h.diff?tr1=1.2&tr2=1.3&r1=text&r2=text
http://savannah.gnu.org/cgi-bin/viewcvs/hurd/hurd-l4/libl4/ia32/l4/bits/vregs.h.diff?tr1=1.3&tr2=1.4&r1=text&r2=text
Patches:
Index: hurd-l4/libl4/ia32/Makefile.am
diff -u hurd-l4/libl4/ia32/Makefile.am:1.1 hurd-l4/libl4/ia32/Makefile.am:1.2
--- hurd-l4/libl4/ia32/Makefile.am:1.1 Sat Jul 26 13:26:09 2003
+++ hurd-l4/libl4/ia32/Makefile.am Mon Sep 22 16:52:07 2003
@@ -1,3 +1,23 @@
+# Makefile.am - Makefile template for libl4/ia32.
+# Copyright (C) 2003 Free Software Foundation, Inc.
+# Written by Marcus Brinkmann.
+#
+# This file is part of the GNU Hurd.
+#
+# The GNU Hurd is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# The GNU Hurd is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
nobase_include_HEADERS = l4/bits/types.h \
l4/bits/math.h l4/bits/vregs.h l4/bits/syscall.h \
l4/bits/stubs.h l4/bits/stubs-init.h \
Index: hurd-l4/libl4/ia32/l4/bits/ipc.h
diff -u hurd-l4/libl4/ia32/l4/bits/ipc.h:1.2
hurd-l4/libl4/ia32/l4/bits/ipc.h:1.3
--- hurd-l4/libl4/ia32/l4/bits/ipc.h:1.2 Mon Sep 22 16:26:57 2003
+++ hurd-l4/libl4/ia32/l4/bits/ipc.h Mon Sep 22 16:52:07 2003
@@ -1,4 +1,4 @@
-/* ipc.h - L4 IPC features for powerpc.
+/* ipc.h - L4 IPC features for ia32.
Copyright (C) 2003 Free Software Foundation, Inc.
Written by Marcus Brinkmann <address@hidden>.
@@ -23,4 +23,6 @@
# error "Never use <l4/bits/ipc.h> directly; include <l4/ipc.h> instead."
#endif
-/* Nothing yet. */
+#define l4_allocate_new_cache_lines 1
+#define l4_do_not_allocate_new_cache_lines 2
+#define l4_allocate_only_new_cache_lines 3
Index: hurd-l4/libl4/ia32/l4/bits/kip.h
diff -u hurd-l4/libl4/ia32/l4/bits/kip.h:1.2
hurd-l4/libl4/ia32/l4/bits/kip.h:1.3
--- hurd-l4/libl4/ia32/l4/bits/kip.h:1.2 Mon Sep 22 16:26:57 2003
+++ hurd-l4/libl4/ia32/l4/bits/kip.h Mon Sep 22 16:52:07 2003
@@ -23,4 +23,5 @@
# error "Never use <l4/bits/kip.h> directly; include <l4/kip.h> instead."
#endif
-/* Nothing yet. */
+/* Kernel features. */
+#define L4_FEATURE_SMALLSPACES "smallspaces"
Index: hurd-l4/libl4/ia32/l4/bits/math.h
diff -u hurd-l4/libl4/ia32/l4/bits/math.h:1.4
hurd-l4/libl4/ia32/l4/bits/math.h:1.5
--- hurd-l4/libl4/ia32/l4/bits/math.h:1.4 Mon Sep 22 16:26:57 2003
+++ hurd-l4/libl4/ia32/l4/bits/math.h Mon Sep 22 16:52:07 2003
@@ -1,4 +1,4 @@
-/* math.h - Math support routines for powerpc.
+/* math.h - Math support routines for ia32.
Copyright (C) 2003 Free Software Foundation, Inc.
Written by Marcus Brinkmann <address@hidden>.
@@ -31,12 +31,11 @@
{
l4_word_t msb;
- /* Count the leading zeros. */
- asm ("cntlzw %[msb], %[data]"
- : [msb] "=r" (msb)
- : "r" (data & -data));
+ __asm__ ("bsr %[data], %[msb]"
+ : [msb] "=r" (msb)
+ : [data] "rm" (data));
- return 32 - msb;
+ return msb + 1;
}
@@ -47,6 +46,9 @@
{
l4_word_t lsb;
- /* x & -x clears all bits in the word except the LSB set. */
- return __l4_msb (data & -data);
+ __asm__ ("bsf %[data], %[lsb]"
+ : [lsb] "=r" (lsb)
+ : [data] "rm" (data));
+
+ return lsb + 1;
}
Index: hurd-l4/libl4/ia32/l4/bits/misc.h
diff -u hurd-l4/libl4/ia32/l4/bits/misc.h:1.2
hurd-l4/libl4/ia32/l4/bits/misc.h:1.3
--- hurd-l4/libl4/ia32/l4/bits/misc.h:1.2 Mon Sep 22 16:26:57 2003
+++ hurd-l4/libl4/ia32/l4/bits/misc.h Mon Sep 22 16:52:07 2003
@@ -1,4 +1,4 @@
-/* misc.h - L4 miscellaneous definitions for powerpc.
+/* misc.h - L4 miscellaneous definitions for ia32.
Copyright (C) 2003 Free Software Foundation, Inc.
Written by Marcus Brinkmann <address@hidden>.
@@ -23,11 +23,8 @@
# error "Never use <l4/bits/misc.h> directly; include <l4/misc.h> instead."
#endif
-#define l4_write_through_memory 1
-#define l4_write_back_memory 2
-#define l4_cache_inhibited_memory 3
-#define l4_cache_enabled_memory 4
-#define l4_global_memory 5
-#define l4_local_memory 6
-#define l4_guarded_memory 7
-#define l4_speculative_memory 8
+#define l4_uncacheable_memory 1
+#define l4_write_combining_memory 2
+#define l4_write_through_memory 5
+#define l4_write_protected_memory 6
+#define l4_write_back_memory 7
Index: hurd-l4/libl4/ia32/l4/bits/space.h
diff -u hurd-l4/libl4/ia32/l4/bits/space.h:1.3
hurd-l4/libl4/ia32/l4/bits/space.h:1.4
--- hurd-l4/libl4/ia32/l4/bits/space.h:1.3 Mon Sep 22 16:26:57 2003
+++ hurd-l4/libl4/ia32/l4/bits/space.h Mon Sep 22 16:52:07 2003
@@ -24,4 +24,68 @@
#endif
-/* Nothing yet. */
+/* IO Fpages. */
+
+typedef _L4_RAW
+(l4_word_t, _L4_STRUCT1
+ ({
+ _L4_BITFIELD4
+ (l4_word_t,
+ _L4_BITFIELD (rights, 4),
+ _L4_BITFIELD (_two, 2),
+ _L4_BITFIELD (log2_size, 6),
+ _L4_BITFIELD_32_64 (base, 16, 48));
+ })) l4_io_fpage_t;
+
+
+static inline l4_fpage_t
+__attribute__((__always_inline__))
+l4_io_fpage (l4_word_t base_address, int size)
+{
+ l4_fpage_t fpage;
+ l4_io_fpage_t io_fpage;
+ l4_word_t msb = __l4_msb (size);
+
+ io_fpage.rights = 0;
+ io_fpage._two = 2;
+ io_fpage.log2_size = (1 << msb) == size ? msb : msb + 1;
+ io_fpage.base = base_address;
+ fpage.raw = io_fpage.raw;
+ return fpage;
+}
+
+
+static inline l4_fpage_t
+__attribute__((__always_inline__))
+l4_io_fpage_log2 (l4_word_t base_address, int log2_size)
+{
+ l4_fpage_t fpage;
+ l4_io_fpage_t io_fpage;
+
+ io_fpage.rights = 0;
+ io_fpage._two = 2;
+ io_fpage.log2_size = log2_size;
+ io_fpage.base = base_address;
+ fpage.raw = io_fpage.raw;
+ return fpage;
+}
+
+
+/* l4_space_control control argument. */
+
+#define L4_LARGE_SPACE 0
+#define L4_SMALL_SPACE (1 << 31)
+
+
+/* LOC and SIZE are in MB. */
+static inline l4_word_t
+__attribute__((__always_inline__))
+l4_small_space (l4_word_t loc, l4_word_t size)
+{
+ l4_word_t small_space = loc >> 1; /* Divide by 2 (MB). */
+ l4_word_t two_pow_p = size >> 2; /* Divide by 4 (MB). */
+
+ /* Make P the LSB of small_space. */
+ small_space = (small_space & ~(two_pow_p - 1)) | two_pow_p;
+ return small_space & 0xff;
+}
Index: hurd-l4/libl4/ia32/l4/bits/stubs.h
diff -u hurd-l4/libl4/ia32/l4/bits/stubs.h:1.2
hurd-l4/libl4/ia32/l4/bits/stubs.h:1.3
--- hurd-l4/libl4/ia32/l4/bits/stubs.h:1.2 Mon Sep 22 16:26:57 2003
+++ hurd-l4/libl4/ia32/l4/bits/stubs.h Mon Sep 22 16:52:07 2003
@@ -1,4 +1,4 @@
-/* stubs.h - L4 system call stubs for powerpc.
+/* stubs.h - L4 system call stubs for ia32.
Copyright (C) 2003 Free Software Foundation, Inc.
Written by Marcus Brinkmann <address@hidden>.
Index: hurd-l4/libl4/ia32/l4/bits/syscall.h
diff -u hurd-l4/libl4/ia32/l4/bits/syscall.h:1.3
hurd-l4/libl4/ia32/l4/bits/syscall.h:1.4
--- hurd-l4/libl4/ia32/l4/bits/syscall.h:1.3 Mon Sep 22 16:26:57 2003
+++ hurd-l4/libl4/ia32/l4/bits/syscall.h Mon Sep 22 16:52:07 2003
@@ -1,4 +1,4 @@
-/* syscall.h - Public interface to the L4 system calls for powerpc.
+/* syscall.h - Public interface to the L4 system calls for ia32.
Copyright (C) 2003 Free Software Foundation, Inc.
Written by Marcus Brinkmann <address@hidden>.
@@ -24,17 +24,6 @@
#endif
-/* These are the clobber registers. R1, R2, R30, R31, and all
- floating point registers are preserved. R3 to R10 are used in
- system calls and thus are not in this list. Up to R17 is used in
- the IPC system calls. */
-#define __L4_PPC_XCLOB "r18", "r19", \
- "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
\
- "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", "xer", "memory"
-#define __L4_PPC_CLOB "r0", "r11", "r12", "r13", "r14", "r15", "r16", \
- "r17", __L4_PPC_XCLOB
-
-
/* Return the pointer to the kernel interface page, the API version,
the API flags, and the kernel ID. */
@@ -43,19 +32,15 @@
l4_kernel_interface (l4_api_version_t *api_version, l4_api_flags_t *api_flags,
l4_kernel_id_t *kernel_id)
{
- register void *kip asm ("r3");
- register l4_word_t version asm ("r4");
- register l4_word_t flags asm ("r5");
- register l4_word_t id asm ("r6");
-
- __asm__ ("tlbia\n"
- : "+r" (kip), "+r" (version), "+r" (flags), "+r" (id)
- :
- : "r3", "r4", "r5", "r6");
-
- *r_version = version;
- *r_flags = flags;
- *r_id = id;
+ void *kip;
+
+ /* The KernelInterface system call is invoked by "lock; nop" and
+ returns a pointer to the kernel interface page in %eax, the API
+ version in %ecx, the API flags in %edx, and the kernel ID in
+ %esi. */
+ __asm__ (" lock; nop\n"
+ : "=a" (kip), "=c" (api_version->raw),
+ "=d" (api_flags->raw), "=S" (kernel_id->raw));
return kip;
}
@@ -63,33 +48,48 @@
static inline void
__attribute__((__always_inline__))
-l4_exchange_registers (l4_thread_id_t *dest_p, l4_word_t *control_p,
- l4_word_t *sp_p, l4_word_t *ip_p, l4_word_t *flags_p,
- l4_word_t *user_handle_p, l4_thread_id_t *pager_p)
-{
- register l4_word_t dest_result asm ("r3") = dest_p->raw;
- register l4_word_t control asm ("r4") = *control_p;
- register l4_word_t sp asm ("r5") = *sp_p;
- register l4_word_t ip asm ("r6") = *ip_p;
- register l4_word_t flags asm ("r7") = *flags_p;
- register l4_word_t user_handle asm ("r8") = *user_handle_p;
- register l4_word_t pager asm ("r9") = pager_p->raw;
-
- __asm__ __volatile__ ("mtctr %[addr]\n"
- "bctrl\n"
- : "+r" (dest_result), "+r" (control),
- "+r" (sp), "+r" (ip), "+r" (flags),
- "+r" (user_handle), "+r" (pager)
- : [addr] "r" (__l4_exchange_register)
- : "r10", __L4_PPC_CLOB);
-
- dest_p->raw = dest_result;
- *control_p = control;
- *sp_p = sp;
- *ip_p = ip;
- *flags_p = flags;
- *user_handle_p = user_handle;
- pager_p->raw = pager;
+l4_exchange_registers (l4_thread_id_t *dest, l4_word_t *control,
+ l4_word_t *sp, l4_word_t *ip, l4_word_t *flags,
+ l4_word_t *user_defined_handle, l4_thread_id_t *pager)
+{
+ /* We can not invoke the system call directly using GCC inline
+ assembler, as the system call requires the PAGER argument to be
+ in %ebp, and that is used by GCC to locate the function arguments
+ on the stack, and there is no other free register we can use to
+ hold the PAGER argument temporarily. So we must pass a pointer
+ to an array of two function arguments in one register, one of
+ them being the PAGER, the other being the one to be stored in the
+ register used to hold the array pointer. */
+ struct
+ {
+ l4_word_t ebp;
+ l4_word_t esi;
+ } regs = { pager->raw, *ip };
+
+ __asm__ __volatile__ ("pushl %%ebp\n"
+ "pushl %%esi\n"
+ /* After saving %ebp and ®s on the stack,
+ set up the remaining system call
+ arguments. */
+ "movl (%%esi), %%ebp\n"
+ "movl 4(%%esi), %%esi\n"
+ "call *__l4_exchange_registers\n"
+
+ /* Temporarily exchange %esi with ®s on the
+ stack and store %ebp. */
+ "xchgl %%esi, (%%esp)\n"
+ "movl %%ebp, (%%esi)\n"
+ /* Pop %esi that was returned from the syscall. */
+ "popl %%esi\n"
+ "popl %%ebp\n"
+ : "=a" (dest->raw), "=c" (*control), "=d" (*sp),
+ "=S" (*ip), "=D" (*flags), "=b" (*user_defined_handle)
+ : "a" (dest->raw), "c" (*control), "d" (*sp),
+ "S" (®s), "D" (*flags), "b" (*user_defined_handle)
+ : "memory");
+
+ pager->raw = regs.ebp;
+ return;
}
@@ -99,21 +99,19 @@
l4_thread_id_t scheduler, l4_thread_id_t pager,
void *utcb_loc)
{
- register l4_word_t dest_result asm ("r3") = dest.raw;
- register l4_word_t space_raw asm ("r4") = space.raw;
- register l4_word_t scheduler_raw asm ("r5") = scheduler.raw;
- register l4_word_t pager_raw asm ("r6") = pager.raw;
- register l4_word_t utcb asm ("r7") = (l4_word_t) utcb_loc;
-
- __asm__ __volatile__ ("mtctr %[addr]\n"
- "bctrl\n"
- : "+r" (dest_result)
- : "r" (space_raw), "r" (scheduler_raw),
- "r" (pager_raw), "r" (utcb),
- [addr] "r" (__l4_thread_control)
- : "r8", "r9", "r10", __L4_PPC_CLOB);
+ l4_word_t result;
+ l4_word_t dummy;
- return dest_result;
+ __asm__ __volatile__ ("push %%ebp\n"
+ "call *__l4_thread_control\n"
+ "pop %%ebp\n"
+ : "=a" (result), "=c" (dummy),
+ "=d" (dummy), "=S" (dummy), "=D" (dummy)
+ : "a" (dest.raw), "c" (pager.raw),
+ "d" (scheduler.raw), "S" (space.raw),
+ "D" (utcb_loc)
+ : "ebx");
+ return result;
}
@@ -121,17 +119,14 @@
__attribute__((__always_inline__))
l4_system_clock (void)
{
- register l4_word_t time_low asm ("r3");
- register l4_word_t time_high asm ("r4");
+ l4_clock_t time;
- __asm__ __volatile__ ("mtctr %[addr]\n"
- "bctrl\n"
- : "=r" (time_low), "=r" (time_high)
- : [addr] "r" (__l4_system_clock)
- : "r5", "r6", "r7", "r8", "r9", "r10",
- __L4_PPC_CLOB);
+ __asm__ __volatile__ ("call *__l4_system_clock"
+ : "=A" (time)
+ :
+ : "ecx", "esi");
- return (((l4_clock_t) time_high) << 32) | time_low;
+ return time;
}
@@ -139,13 +134,9 @@
__attribute__((__always_inline__))
l4_thread_switch (l4_thread_id_t dest)
{
- register l4_word_t dest_raw asm ("r3") = dest.raw;
-
- __asm__ __volatile__ ("mtctr %[addr]\n"
- "bctrl\n"
+ __asm__ __volatile__ ("call *__l4_thread_switch"
:
- : "r" (dest_raw), [addr] "r" (__l4_thread_switch)
- : __L4_PPC_CLOB);
+ : "a" (dest.raw));
}
@@ -155,21 +146,19 @@
l4_word_t proc_control, l4_word_t prio,
l4_word_t preempt_control, l4_word_t *old_time_control)
{
- register l4_word_t dest_result asm ("r3") = dest.raw;
- register l4_word_t time asm ("r4") = time_control;
- register l4_word_t proc asm ("r5") = proc_control;
- register l4_word_t priority asm ("r6") = prio;
- register l4_word_t preempt asm ("r7") = preempt_control;
-
- __asm__ __volatile__ ("mtctr %[addr]\n"
- "bctrl\n"
- : "+r" (dest_result), "+r" (time)
- : "r" (proc), "r" (priority), "r" (preempt),
- [addr] "r" (__l4_schedule)
- : "r8", "r9", "r10", __L4_PPC_CLOB);
+ l4_word_t result;
+ l4_word_t dummy;
- *old_time_control = time;
- return dest_result;
+ __asm__ __volatile__ ("push %%ebp\n"
+ "call *__l4_schedule\n"
+ "pop %%ebp\n"
+ : "=a" (result), "=d" (*old_time_control),
+ "=c" (dummy), "=S" (dummy), "=D" (dummy)
+ : "a" (dest), "c" (prio), "d" (time_control),
+ "S" (proc_control), "D" (preempt_control)
+ : "ebx");
+
+ return result;
}
@@ -177,14 +166,19 @@
__attribute__((__always_inline__))
l4_unmap (l4_word_t control)
{
- register l4_word_t ctrl asm ("r3") = control;
-
- __asm__ __volatile__ ("mtctr %[addr]\n"
- "bctrl\n"
- :
- : "r" (ctrl), [addr] "r" (__l4_unmap)
- : "r4", "r5", "r6", "r7", "r8", "r9", "r10",
- __L4_PPC_CLOB);
+ l4_word_t mr0;
+ l4_word_t utcb;
+ l4_word_t dummy;
+
+ l4_store_mr (0, &mr0);
+ utcb = (l4_word_t) __l4_utcb ();
+
+ __asm__ __volatile__ ("push %%ebp\n"
+ "call *__l4_unmap\n"
+ "pop %%ebp\n"
+ : "=a" (mr0), "=c" (dummy), "=d" (dummy)
+ : "a" (mr0), "c" (utcb), "d" (control)
+ : "esi", "edi", "ebx");
}
@@ -194,21 +188,19 @@
l4_fpage_t kip_area, l4_fpage_t utcb_area,
l4_thread_id_t redirector, l4_word_t *old_control)
{
- register l4_word_t space_result asm ("r3") = dest.raw;
- register l4_word_t ctrl asm ("r4") = control;
- register l4_word_t kip asm ("r5") = kip_area;
- register l4_word_t utcb asm ("r6") = utcb_area;
- register l4_word_t redir asm ("r7") = redirector;
-
- __asm__ __volatile__ ("mtctr %[addr]\n"
- "bctrl\n"
- : "+r" (space_result), "+r" (ctrl)
- : "r" (kip), "r" (utcb), "r" (redir),
- [addr] "r" (__l4_space_control)
- : "r8", "r9", "r10", __L4_PPC_CLOB);
+ l4_word_t result;
+ l4_word_t dummy;
- *old_control = ctrl;
- return space_result;
+ __asm__ __volatile__ ("push %%ebp\n"
+ "call *__l4_space_control\n"
+ "pop %%ebp\n"
+ : "=a" (result), "=c" (*old_control),
+ "=d" (dummy), "=S" (dummy), "=D" (dummy)
+ : "a" (space.raw), "c" (control),
+ "d" (kip_area.raw), "S" (utcb_area.raw),
+ "D" (redirector.raw)
+ : "ebx");
+ return result;
}
@@ -217,45 +209,33 @@
l4_ipc (l4_thread_id_t to, l4_thread_id_t from_spec,
l4_word_t timeouts, l4_thread_id_t *from)
{
- l4_word_t *mr = __l4_utcb () + __L4_UTCB_MR0;
- register l4_word_t mr9 asm ("r0") = mr[9];
- register l4_word_t mr1 asm ("r3") = mr[1];
- register l4_word_t mr2 asm ("r4") = mr[2];
- register l4_word_t mr3 asm ("r5") = mr[3];
- register l4_word_t mr4 asm ("r6") = mr[4];
- register l4_word_t mr5 asm ("r7") = mr[5];
- register l4_word_t mr6 asm ("r8") = mr[6];
- register l4_word_t mr7 asm ("r9") = mr[7];
- register l4_word_t mr8 asm ("r10") = mr[8];
- register l4_word_t mr0 asm ("r14") = mr[0];
- register l4_word_t to_raw asm ("r15") = to.raw;
- register l4_word_t from_spec_raw asm ("r16") = from_spec.raw;
- register l4_word_t time_outs asm ("r17") = timeouts;
-
- __asm__ __volatile__ ("mtctr %[addr]\n"
- "bctrl\n"
- : "+r" (mr9), "+r" (mr1), "+r" (mr2), "+r" (mr3),
- "+r" (mr4), "+r" (mr5), "+r" (mr6), "+r" (mr7),
- "+r" (mr8), "+r" (mr0), "+r" (from_spec_raw),
- : "r" (to_raw), "r" (time_outs),
- [addr] "r" (__l4_ipc)
- : "r11", "r12", "r13", __L4_PPC_XCLOB);
-
+ l4_word_t mr[2];
+ l4_word_t utcb;
+ l4_msg_tag_t tag;
+ l4_thread_id_t result;
+ l4_word_t dummy;
+
+ utcb = (l4_word_t) __l4_utcb ();
+ l4_store_mr (0, &tag.raw);
+ l4_store_mr (1, &mr[0]);
+ l4_store_mr (2, &mr[1]);
+
+ __asm__ __volatile__ ("push %%ebp\n"
+ "call *__l4_ipc\n"
+ "movl %%ebp, %%ecx\n"
+ "pop %%ebp\n"
+ : "=a" (result.raw), "=c" (mr[1]), "=d" (dummy),
+ "=S" (tag.raw), "=b" (mr[0])
+ : "a" (to.raw), "c" (timeouts), "d" (from_spec.raw),
+ "S" (tag.raw), "D" (utcb));
/* FIXME: Make it so that we can use l4_is_nilthread? */
- if (from_spec_raw)
+ if (from_spec.raw)
{
- from->raw = from_spec_raw;
- mr[1] = mr1;
- mr[2] = mr2;
- mr[3] = mr3;
- mr[4] = mr4;
- mr[5] = mr5;
- mr[6] = mr6;
- mr[7] = mr7;
- mr[8] = mr8;
- mr[9] = mr9;
+ *from = result;
+ l4_load_mr (1, mr[0]);
+ l4_load_mr (2, mr[1]);
}
- return (l4_msg_tag_t) { .raw = mr0 };
+ return tag;
}
@@ -264,67 +244,53 @@
l4_lipc (l4_thread_id_t to, l4_thread_id_t from_spec,
l4_word_t timeouts, l4_thread_id_t *from)
{
- l4_word_t *mr = __l4_utcb () + __L4_UTCB_MR0;
- register l4_word_t mr9 asm ("r0") = mr[9];
- register l4_word_t mr1 asm ("r3") = mr[1];
- register l4_word_t mr2 asm ("r4") = mr[2];
- register l4_word_t mr3 asm ("r5") = mr[3];
- register l4_word_t mr4 asm ("r6") = mr[4];
- register l4_word_t mr5 asm ("r7") = mr[5];
- register l4_word_t mr6 asm ("r8") = mr[6];
- register l4_word_t mr7 asm ("r9") = mr[7];
- register l4_word_t mr8 asm ("r10") = mr[8];
- register l4_word_t mr0 asm ("r14") = mr[0];
- register l4_word_t to_raw asm ("r15") = to.raw;
- register l4_word_t from_spec_raw asm ("r16") = from_spec.raw;
- register l4_word_t time_outs asm ("r17") = timeouts;
-
- __asm__ __volatile__ ("mtctr %[addr]\n"
- "bctrl\n"
- : "+r" (mr9), "+r" (mr1), "+r" (mr2), "+r" (mr3),
- "+r" (mr4), "+r" (mr5), "+r" (mr6), "+r" (mr7),
- "+r" (mr8), "+r" (mr0), "+r" (from_spec_raw),
- : "r" (to_raw), "r" (time_outs),
- [addr] "r" (__l4_lipc)
- : "r11", "r12", "r13", __L4_PPC_XCLOB);
-
+ l4_word_t mr[2];
+ l4_word_t utcb;
+ l4_msg_tag_t tag;
+ l4_thread_id_t result;
+ l4_word_t dummy;
+
+ utcb = (l4_word_t) __l4_utcb ();
+ l4_store_mr (0, &tag.raw);
+ l4_store_mr (1, &mr[0]);
+ l4_store_mr (2, &mr[1]);
+
+ __asm__ __volatile__ ("push %%ebp\n"
+ "call *__l4_lipc\n"
+ "movl %%ebp, %%ecx\n"
+ "pop %%ebp\n"
+ : "=a" (result.raw), "=c" (mr[1]), "=d" (dummy),
+ "=S" (tag.raw), "=b" (mr[0])
+ : "a" (to.raw), "c" (timeouts), "d" (from_spec.raw),
+ "S" (tag.raw), "D" (utcb));
/* FIXME: Make it so that we can use l4_is_nilthread? */
- if (from_spec_raw)
+ if (from_spec.raw)
{
- from->raw = from_spec_raw;
- mr[1] = mr1;
- mr[2] = mr2;
- mr[3] = mr3;
- mr[4] = mr4;
- mr[5] = mr5;
- mr[6] = mr6;
- mr[7] = mr7;
- mr[8] = mr8;
- mr[9] = mr9;
+ *from = result;
+ l4_load_mr (1, mr[0]);
+ l4_load_mr (2, mr[1]);
}
- return (l4_msg_tag_t) { .raw = mr0 };
+ return tag;
}
static inline l4_word_t
__attribute__((__always_inline__))
-l4_processor_control (l4_word_t proc, l4_word_t int_freq,
+l4_processor_control (l4_word_t proc, l4_word_t control, l4_word_t int_freq,
l4_word_t ext_freq, l4_word_t voltage)
{
- register l4_word_t proc_result asm ("r3") = proc;
- register l4_word_t internal_freq asm ("r4") = int_freq;
- register l4_word_t external_freq asm ("r5") = ext_freq;
- register l4_word_t volt asm ("r6") = voltage;
-
- __asm__ __volatile__ ("mtctr %[addr]\n"
- "bctrl\n"
- : "+r" (proc_result)
- : "r" (internal_freq), "r" (external_freq),
- "r" (volt),
- [addr] "r" (__l4_processor_control)
- : "r7", "r8", "r9", "r10", __L4_PPC_CLOB);
+ l4_word_t result;
+ l4_word_t dummy;
- return proc_result;
+ __asm__ __volatile__ ("push %%ebp\n"
+ "call *__l4_processor_control\n"
+ "pop %%ebp\n"
+ : "=a" (result), "=c" (dummy),
+ "=d" (dummy), "=S" (dummy), "=D" (dummy)
+ : "a" (proc), "c" (control), "d" (int_freq),
+ "S" (ext_freq), "D" (voltage)
+ : "ebx");
+ return result;
}
@@ -332,17 +298,17 @@
__attribute__((__always_inline__))
l4_memory_control (l4_word_t control, l4_word_t *attributes)
{
- register l4_word_t ctrl asm ("r3") = control;
- register l4_word_t attr0 asm ("r4") = attributes[0];
- register l4_word_t attr1 asm ("r5") = attributes[1];
- register l4_word_t attr2 asm ("r6") = attributes[2];
- register l4_word_t attr3 asm ("r7") = attributes[3];
+ l4_word_t tag;
+ l4_word_t dummy;
- __asm__ __volatile__ ("mtctr %[addr]\n"
- "bctrl\n"
- :
- : "r" (ctrl), "r" (attr0), "r" (attr1),
- "r" (attr2), "r" (attr3),
- [addr] "r" (__l4_memory_control)
- : "r8", "r9", "r10", __L4_PPC_CLOB);
+ l4_store_mr (0, &tag);
+
+ __asm__ __volatile__ ("push %%ebp\n"
+ "call *__l4_memory_control\n"
+ "pop %%ebp\n"
+ : "=a" (dummy), "=c" (dummy), "=d" (dummy),
+ "=S" (dummy), "=D" (dummy), "=b" (dummy)
+ : "a" (tag), "c" (control), "d" (attributes[0]),
+ "S" (attributes[1]), "D" (attributes[2]),
+ "b" (attributes[3]));
}
Index: hurd-l4/libl4/ia32/l4/bits/types.h
diff -u hurd-l4/libl4/ia32/l4/bits/types.h:1.2
hurd-l4/libl4/ia32/l4/bits/types.h:1.3
--- hurd-l4/libl4/ia32/l4/bits/types.h:1.2 Mon Sep 22 16:26:57 2003
+++ hurd-l4/libl4/ia32/l4/bits/types.h Mon Sep 22 16:52:07 2003
@@ -1,4 +1,4 @@
-/* types.h - L4 machine type definitions for powerpc.
+/* types.h - L4 machine type definitions for ia32.
Copyright (C) 2003 Free Software Foundation, Inc.
Written by Marcus Brinkmann <address@hidden>.
@@ -23,8 +23,8 @@
# error "Never use <l4/bits/types.h> directly; include <l4/types.h> instead."
#endif
-/* PowerPC has 32 bits per word. */
+/* ia32 has 32 bits per word. */
#define L4_WORDSIZE L4_WORDSIZE_32
-/* PowerPC is big-endian. */
-#define L4_BYTE_ORDER L4_BIG_ENDIAN
+/* ia32 is little-endian. */
+#define L4_BYTE_ORDER L4_LITTLE_ENDIAN
Index: hurd-l4/libl4/ia32/l4/bits/vregs.h
diff -u hurd-l4/libl4/ia32/l4/bits/vregs.h:1.3
hurd-l4/libl4/ia32/l4/bits/vregs.h:1.4
--- hurd-l4/libl4/ia32/l4/bits/vregs.h:1.3 Mon Sep 22 16:26:57 2003
+++ hurd-l4/libl4/ia32/l4/bits/vregs.h Mon Sep 22 16:52:07 2003
@@ -1,4 +1,4 @@
-/* vregs.h - L4 virtual registers for powerpc.
+/* vregs.h - L4 virtual registers for ia32.
Copyright (C) 2003 Free Software Foundation, Inc.
Written by Marcus Brinkmann <address@hidden>.
@@ -31,7 +31,7 @@
{
l4_word_t *utcb;
- __asm__ ("mr %[utcb], %%r2"
+ __asm__ ("movl %%gs:0, %[utcb]"
: [utcb] "=r" (utcb));
return utcb;
@@ -164,7 +164,10 @@
/* The second byte in the flags field contains the coprocessor
flags. */
- utcb[__L4_UTCB_FLAGS] &= ~(1 << (8 + n));
+ __asm__ ("andl %[mask], %[where]"
+ :
+ : [mask] "ir" (~(1 << (8 + n))),
+ [where] "m" (utcb[__L4_UTCB_FLAGS]));
}
@@ -176,7 +179,10 @@
/* The second byte in the flags field contains the coprocessor
flags. */
- utcb[__L4_UTCB_FLAGS] |= 1 << (8 + n);
+ __asm__ ("orl %[mask], %[where]"
+ :
+ : [mask] "ir" (1 << (8 + n)),
+ [where] "m" (utcb[__L4_UTCB_FLAGS]));
}
@@ -185,12 +191,14 @@
l4_disable_preemption_fault_exception (void)
{
l4_word_t *utcb = __l4_utcb ();
- l4_word_t result;
+ l4_uint8_t result;
/* The first byte in the flags field contains the preemption
- flags. The sixth bit is the signal bit. */
- result = (utcb[__L4_UTCB_FLAGS] >> 5) & 1;
- utcb[__L4_UTCB_FLAGS] &= ~(1 << 5);
+ flags. The sixth bit is the signal bit*/
+ __asm__ ("btr %[offset], %[base]\n"
+ "setc %[result]"
+ : [result] "=r" (result)
+ : [offset] "i" (5), [base] "m" (utcb[__L4_UTCB_FLAGS]));
return result;
}
@@ -201,12 +209,14 @@
l4_enable_preemption_fault_exception (void)
{
l4_word_t *utcb = __l4_utcb ();
- l4_word_t result;
+ l4_uint8_t result;
/* The first byte in the flags field contains the preemption
flags. The sixth bit is the signal flag. */
- result = (utcb[__L4_UTCB_FLAGS] >> 5) & 1;
- utcb[__L4_UTCB_FLAGS] |= 1 << 5;
+ __asm__ ("bts %[offset], %[base]\n"
+ "setc %[result]"
+ : [result] "=r" (result)
+ : [offset] "i" (5), [base] "m" (utcb[__L4_UTCB_FLAGS]));
return result;
}
@@ -217,12 +227,14 @@
l4_disable_preemption (void)
{
l4_word_t *utcb = __l4_utcb ();
- l4_word_t result;
+ l4_uint8_t result;
/* The first byte in the flags field contains the preemption
flags. The seventh bit is the delay flag. */
- result = (utcb[__L4_UTCB_FLAGS] >> 6) & 1;
- utcb[__L4_UTCB_FLAGS] &= ~(1 << 6);
+ __asm__ ("btr %[offset], %[base]\n"
+ "setc %[result]"
+ : [result] "=r" (result)
+ : [offset] "i" (6), [base] "m" (utcb[__L4_UTCB_FLAGS]));
return result;
}
@@ -233,12 +245,14 @@
l4_enable_preemption (void)
{
l4_word_t *utcb = __l4_utcb ();
- l4_word_t result;
+ l4_uint8_t result;
/* The first byte in the flags field contains the preemption
flags. The seventh bit is the delay flag. */
- result = (utcb[__L4_UTCB_FLAGS] >> 6) & 1;
- utcb[__L4_UTCB_FLAGS] |= 1 << 6;
+ __asm__ ("bts %[offset], %[base]\n"
+ "setc %[result]"
+ : [result] "=r" (result)
+ : [offset] "i" (6), [base] "m" (utcb[__L4_UTCB_FLAGS]));
return result;
}
@@ -249,10 +263,14 @@
l4_preemption_pending (void)
{
l4_word_t *utcb = __l4_utcb ();
- l4_word_t result;
+ l4_uint8_t result;
- result = (utcb[__L4_UTCB_FLAGS] >> 7) & 1;
- utcb[__L4_UTCB_FLAGS] &= ~(1 << 7);
+ /* The first byte in the flags field contains the preemption
+ flags. The eighth bit is the pending flag. */
+ __asm__ ("btr %[offset], %[base]\n"
+ "setc %[result]"
+ : [result] "=r" (result)
+ : [offset] "i" (7), [base] "m" (utcb[__L4_UTCB_FLAGS]));
return result;
}
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