[Commit-gnuradio] [gnuradio] 21/148: put 64 bit timer for vita49 on the settings bus

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nwest pushed a commit to annotated tag old_usrp_devel_udp
in repository gnuradio.

commit 240d7c5c8e8f1722abb0baffecf0f007576a00aa
Author: Matt Ettus <address@hidden>
Date:   Thu Nov 5 13:41:20 2009 -0800

    put 64 bit timer for vita49 on the settings bus
---
 usrp2/firmware/lib/memory_map.h  | 12 +++++++++++-
 usrp2/fpga/timing/time_64bit.v   | 12 +++++-------
 usrp2/fpga/top/u2_core/u2_core.v | 12 +++++++++++-
 usrp2/fpga/top/u2_rev3/Makefile  |  1 +
 4 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/usrp2/firmware/lib/memory_map.h b/usrp2/firmware/lib/memory_map.h
index 0d0cf04..b049371 100644
--- a/usrp2/firmware/lib/memory_map.h
+++ b/usrp2/firmware/lib/memory_map.h
@@ -297,7 +297,7 @@ hwconfig_wishbone_divisor(void)
 #define BUFFER_POOL_CTRL_BASE   0xD500
 #define DSP_TX_BASE             0xD600
 #define DSP_RX_BASE             0xD680
-
+#define TIME64                  0xD700
 #define LAST_SETTING_REG        0xD7FC // last valid setting register
 
 // --- buffer pool control regs ---
@@ -508,6 +508,16 @@ typedef struct {
   (((num_lines) << 9) | ((lines_per_frame) & 0x1ff) \
    | (((now) & 0x1) << 31) | (((chain) & 0x1) << 30))
 
+// ----------------------------------------------------------------
+// VITA49 64 bit time
+typedef struct {
+  volatile uint32_t    secs;   // value to set absolute secs to on next PPS
+  volatile uint32_t    ticks;  // value to set absolute ticks to on next PPS
+} sr_time64_t;
+
+#define sr_time64 ((sr_time64_t *) TIME64
+
+
 /* 
  * --- ethernet tx protocol engine regs (write only) ---
  *
diff --git a/usrp2/fpga/timing/time_64bit.v b/usrp2/fpga/timing/time_64bit.v
index c0a846e..ab0c12b 100644
--- a/usrp2/fpga/timing/time_64bit.v
+++ b/usrp2/fpga/timing/time_64bit.v
@@ -9,10 +9,13 @@ module time_64bit
      output [63:0] vita_time
      );
 
-   localparam     NEXT_TICKS = 0;
-   localparam     NEXT_SECS = 1;   
+   localparam     NEXT_TICKS = 1;
+   localparam     NEXT_SECS = 0;   
    localparam     ROLLOVER = TICKS_PER_SEC - 1;           
    
+   reg [31:0]     seconds;
+   reg [31:0]     ticks;
+   wire           end_of_second;
    assign         vita_time = {seconds,ticks};
    
    wire [31:0]            next_ticks_preset;
@@ -28,11 +31,6 @@ module time_64bit
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig));
    
-   reg [31:0]     seconds;
-   reg [31:0]     ticks;
-   
-   wire           end_of_second;
-   
    always @(posedge clk)
      if(rst)
        set_on_next_pps <= 0;
diff --git a/usrp2/fpga/top/u2_core/u2_core.v b/usrp2/fpga/top/u2_core/u2_core.v
old mode 100755
new mode 100644
index fd17a10..5b272c3
--- a/usrp2/fpga/top/u2_core/u2_core.v
+++ b/usrp2/fpga/top/u2_core/u2_core.v
@@ -135,6 +135,8 @@ module u2_core
    input sim_mode,
    input [3:0] clock_divider
    );
+
+   localparam SR_TIME64 = 192;
    
    wire [7:0]  set_addr;
    wire [31:0]         set_data;
@@ -159,6 +161,7 @@ module u2_core
    wire        serdes_link_up;
    wire        epoch;
    wire [31:0]         irq;
+   wire [63:0]         vita_time;
    
    // 
///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
@@ -560,7 +563,7 @@ module u2_core
       
.fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
       .debug_rx(debug_rx) );
    
-   // dummy_rx dsp_core_rx
+   // dumkmy_rx dsp_core_rx
    dsp_core_rx dsp_core_rx
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
@@ -631,6 +634,13 @@ module u2_core
    assign      RAM_CE1n = 0;
    assign      RAM_D[17:16] = 2'bzz;
    
+   // /////////////////////////////////////////////////////////////////////////
+   // VITA Timing
+
+   time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
+     (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb), .set_addr(set_addr), 
.set_data(set_data),
+      .pps(pps_o), .vita_time(vita_time));
+   
    // 
/////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
    
diff --git a/usrp2/fpga/top/u2_rev3/Makefile b/usrp2/fpga/top/u2_rev3/Makefile
index 4358d7c..8b18550 100644
--- a/usrp2/fpga/top/u2_rev3/Makefile
+++ b/usrp2/fpga/top/u2_rev3/Makefile
@@ -171,6 +171,7 @@ serdes/serdes_fc_rx.v \
 serdes/serdes_fc_tx.v \
 serdes/serdes_rx.v \
 serdes/serdes_tx.v \
+timing/time_64bit.v \
 timing/time_receiver.v \
 timing/time_sender.v \
 timing/time_sync.v \