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[Commit-gnuradio] r10571 - usrp-hw/trunk/sym/xilinx
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From: |
jblum |
|
Subject: |
[Commit-gnuradio] r10571 - usrp-hw/trunk/sym/xilinx |
|
Date: |
Fri, 6 Mar 2009 18:10:14 -0700 (MST) |
Author: jblum
Date: 2009-03-06 18:10:14 -0700 (Fri, 06 Mar 2009)
New Revision: 10571
Added:
usrp-hw/trunk/sym/xilinx/XC3S1400AFG484.csv
usrp-hw/trunk/sym/xilinx/xilinxgen-XC3S1400AFG484
usrp-hw/trunk/sym/xilinx/xilinxgen-XC3S1400AFT256
Removed:
usrp-hw/trunk/sym/xilinx/xilinxgen256
Modified:
usrp-hw/trunk/sym/xilinx/Makefile
Log:
added XC3S1400AFG484
Modified: usrp-hw/trunk/sym/xilinx/Makefile
===================================================================
--- usrp-hw/trunk/sym/xilinx/Makefile 2009-03-06 22:08:43 UTC (rev 10570)
+++ usrp-hw/trunk/sym/xilinx/Makefile 2009-03-07 01:10:14 UTC (rev 10571)
@@ -3,29 +3,31 @@
TRAGESYM=tragesym
SRCFILES = \
-xc3s1400aft256-BOTCLK.src xc3sd3400afg676-CFG.src xc3sXX00fg456-CLK.src
xc5v-ff1136big-BANK15.src xc5v-ff1136small-BANK120.src \
-xc3s1400aft256-CFG.src xc3sd3400afg676-IO0.src xc3sXX00fg456-IO0.src
xc5v-ff1136big-BANK17.src xc5v-ff1136small-BANK122.src \
-xc3s1400aft256-IO0.src xc3sd3400afg676-IO1.src xc3sXX00fg456-IO1.src
xc5v-ff1136big-BANK18.src xc5v-ff1136small-BANK12.src \
-xc3s1400aft256-IO1.src xc3sd3400afg676-IO2.src xc3sXX00fg456-IO2.src
xc5v-ff1136big-BANK19.src xc5v-ff1136small-BANK13.src \
-xc3s1400aft256-IO2.src xc3sd3400afg676-IO3.src xc3sXX00fg456-IO3.src
xc5v-ff1136big-BANK1.src xc5v-ff1136small-BANK15.src \
-xc3s1400aft256-IO3.src xc3sd3400afg676-JTAG.src xc3sXX00fg456-IO4.src
xc5v-ff1136big-BANK20.src xc5v-ff1136small-BANK17.src \
-xc3s1400aft256-JTAG.src xc3sd3400afg676-LHCLK.src xc3sXX00fg456-IO5.src
xc5v-ff1136big-BANK21.src xc5v-ff1136small-BANK18.src \
-xc3s1400aft256-LHCLK.src xc3sd3400afg676-PWR.src xc3sXX00fg456-IO6.src
xc5v-ff1136big-BANK22.src xc5v-ff1136small-BANK19.src \
-xc3s1400aft256-PWR.src xc3sd3400afg676-RHCLK.src xc3sXX00fg456-IO7.src
xc5v-ff1136big-BANK23.src xc5v-ff1136small-BANK1.src \
-xc3s1400aft256-RHCLK.src xc3sd3400afg676-TOPCLK.src xc3sXX00fg456-JTAG.src
xc5v-ff1136big-BANK25.src xc5v-ff1136small-BANK20.src \
-xc3s1400aft256-TOPCLK.src xc3sXX00fg320-CFG.src xc3sXX00fg456-PWR.src
xc5v-ff1136big-BANK2.src xc5v-ff1136small-BANK21.src \
-xc3sd1800acs484-BOTCLK.src xc3sXX00fg320-CLK.src
xc5v-ff1136big-BANK0.src xc5v-ff1136big-BANK3.src
xc5v-ff1136small-BANK22.src \
-xc3sd1800acs484-CFG.src xc3sXX00fg320-IO0.src
xc5v-ff1136big-BANK112.src xc5v-ff1136big-BANK4.src
xc5v-ff1136small-BANK23.src \
-xc3sd1800acs484-IO0.src xc3sXX00fg320-IO1.src
xc5v-ff1136big-BANK114.src xc5v-ff1136big-BANK5.src
xc5v-ff1136small-BANK25.src \
-xc3sd1800acs484-IO1.src xc3sXX00fg320-IO2.src
xc5v-ff1136big-BANK116.src xc5v-ff1136big-BANK6.src
xc5v-ff1136small-BANK2.src \
-xc3sd1800acs484-IO2.src xc3sXX00fg320-IO3.src
xc5v-ff1136big-BANK118.src xc5v-ff1136big-OTHER.src
xc5v-ff1136small-BANK3.src \
-xc3sd1800acs484-IO3.src xc3sXX00fg320-IO4.src
xc5v-ff1136big-BANK11.src xc5v-ff1136big-PWR.src
xc5v-ff1136small-BANK4.src \
-xc3sd1800acs484-JTAG.src xc3sXX00fg320-IO5.src
xc5v-ff1136big-BANK120.src xc5v-ff1136small-BANK0.src
xc5v-ff1136small-BANK5.src \
-xc3sd1800acs484-LHCLK.src xc3sXX00fg320-IO6.src
xc5v-ff1136big-BANK122.src xc5v-ff1136small-BANK112.src
xc5v-ff1136small-BANK6.src \
-xc3sd1800acs484-PWR.src xc3sXX00fg320-IO7.src
xc5v-ff1136big-BANK124.src xc5v-ff1136small-BANK114.src
xc5v-ff1136small-OTHER.src \
-xc3sd1800acs484-RHCLK.src xc3sXX00fg320-JTAG.src
xc5v-ff1136big-BANK126.src xc5v-ff1136small-BANK116.src
xc5v-ff1136small-PWR.src \
-xc3sd1800acs484-TOPCLK.src xc3sXX00fg320-PWR.src
xc5v-ff1136big-BANK12.src xc5v-ff1136small-BANK118.src \
-xc3sd3400afg676-BOTCLK.src xc3sXX00fg456-CFG.src
xc5v-ff1136big-BANK13.src xc5v-ff1136small-BANK11.src
+xc3s1400afg484-BOTCLK.src xc3sd1800acs484-IO1.src xc3sXX00fg320-IO4.src
xc5v-ff1136big-BANK122.src xc5v-ff1136small-BANK116.src \
+xc3s1400afg484-CFG.src xc3sd1800acs484-IO2.src xc3sXX00fg320-IO5.src
xc5v-ff1136big-BANK124.src xc5v-ff1136small-BANK118.src \
+xc3s1400afg484-IO0.src xc3sd1800acs484-IO3.src xc3sXX00fg320-IO6.src
xc5v-ff1136big-BANK126.src xc5v-ff1136small-BANK11.src \
+xc3s1400afg484-IO1.src xc3sd1800acs484-JTAG.src xc3sXX00fg320-IO7.src
xc5v-ff1136big-BANK12.src xc5v-ff1136small-BANK120.src \
+xc3s1400afg484-IO2.src xc3sd1800acs484-LHCLK.src xc3sXX00fg320-JTAG.src
xc5v-ff1136big-BANK13.src xc5v-ff1136small-BANK122.src \
+xc3s1400afg484-IO3.src xc3sd1800acs484-PWR.src xc3sXX00fg320-PWR.src
xc5v-ff1136big-BANK15.src xc5v-ff1136small-BANK12.src \
+xc3s1400afg484-JTAG.src xc3sd1800acs484-RHCLK.src xc3sXX00fg456-CFG.src
xc5v-ff1136big-BANK17.src xc5v-ff1136small-BANK13.src \
+xc3s1400afg484-LHCLK.src xc3sd1800acs484-TOPCLK.src xc3sXX00fg456-CLK.src
xc5v-ff1136big-BANK18.src xc5v-ff1136small-BANK15.src \
+xc3s1400afg484-PWR.src xc3sd3400afg676-BOTCLK.src xc3sXX00fg456-IO0.src
xc5v-ff1136big-BANK19.src xc5v-ff1136small-BANK17.src \
+xc3s1400afg484-RHCLK.src xc3sd3400afg676-CFG.src xc3sXX00fg456-IO1.src
xc5v-ff1136big-BANK1.src xc5v-ff1136small-BANK18.src \
+xc3s1400afg484-TOPCLK.src xc3sd3400afg676-IO0.src xc3sXX00fg456-IO2.src
xc5v-ff1136big-BANK20.src xc5v-ff1136small-BANK19.src \
+xc3s1400aft256-BOTCLK.src xc3sd3400afg676-IO1.src xc3sXX00fg456-IO3.src
xc5v-ff1136big-BANK21.src xc5v-ff1136small-BANK1.src \
+xc3s1400aft256-CFG.src xc3sd3400afg676-IO2.src xc3sXX00fg456-IO4.src
xc5v-ff1136big-BANK22.src xc5v-ff1136small-BANK20.src \
+xc3s1400aft256-IO0.src xc3sd3400afg676-IO3.src xc3sXX00fg456-IO5.src
xc5v-ff1136big-BANK23.src xc5v-ff1136small-BANK21.src \
+xc3s1400aft256-IO1.src xc3sd3400afg676-JTAG.src xc3sXX00fg456-IO6.src
xc5v-ff1136big-BANK25.src xc5v-ff1136small-BANK22.src \
+xc3s1400aft256-IO2.src xc3sd3400afg676-LHCLK.src xc3sXX00fg456-IO7.src
xc5v-ff1136big-BANK2.src xc5v-ff1136small-BANK23.src \
+xc3s1400aft256-IO3.src xc3sd3400afg676-PWR.src xc3sXX00fg456-JTAG.src
xc5v-ff1136big-BANK3.src xc5v-ff1136small-BANK25.src \
+xc3s1400aft256-JTAG.src xc3sd3400afg676-RHCLK.src xc3sXX00fg456-PWR.src
xc5v-ff1136big-BANK4.src xc5v-ff1136small-BANK2.src \
+xc3s1400aft256-LHCLK.src xc3sd3400afg676-TOPCLK.src
xc5v-ff1136big-BANK0.src xc5v-ff1136big-BANK5.src
xc5v-ff1136small-BANK3.src \
+xc3s1400aft256-PWR.src xc3sXX00fg320-CFG.src
xc5v-ff1136big-BANK112.src xc5v-ff1136big-BANK6.src
xc5v-ff1136small-BANK4.src \
+xc3s1400aft256-RHCLK.src xc3sXX00fg320-CLK.src
xc5v-ff1136big-BANK114.src xc5v-ff1136big-OTHER.src
xc5v-ff1136small-BANK5.src \
+xc3s1400aft256-TOPCLK.src xc3sXX00fg320-IO0.src
xc5v-ff1136big-BANK116.src xc5v-ff1136big-PWR.src
xc5v-ff1136small-BANK6.src \
+xc3sd1800acs484-BOTCLK.src xc3sXX00fg320-IO1.src
xc5v-ff1136big-BANK118.src xc5v-ff1136small-BANK0.src
xc5v-ff1136small-OTHER.src \
+xc3sd1800acs484-CFG.src xc3sXX00fg320-IO2.src
xc5v-ff1136big-BANK11.src xc5v-ff1136small-BANK112.src
xc5v-ff1136small-PWR.src \
+xc3sd1800acs484-IO0.src xc3sXX00fg320-IO3.src
xc5v-ff1136big-BANK120.src xc5v-ff1136small-BANK114.src
SYMFILES=$(SRCFILES:.src=.sym)
@@ -38,7 +40,8 @@
./xilinxgen1136-small
./xilinxgen456
./xilinxgen676
- ./xilinxgen256
+ ./xilinxgen-XC3S1400AFT256
+ ./xilinxgen-XC3S1400AFG484
clean:
$(RM) *.src *.sym
Added: usrp-hw/trunk/sym/xilinx/XC3S1400AFG484.csv
===================================================================
--- usrp-hw/trunk/sym/xilinx/XC3S1400AFG484.csv (rev 0)
+++ usrp-hw/trunk/sym/xilinx/XC3S1400AFG484.csv 2009-03-07 01:10:14 UTC (rev
10571)
@@ -0,0 +1,485 @@
+PIN,XC3S1400AFG484,BANK,TYPE,DIFF_PAIR,ROW,ROW_#,COLUMN
+A1,GND,GND,GND,,A,1,1
+A2,IO_L36N_0/PUDC_B,0,DUAL,TRUE,A,1,2
+A3,IO_L33P_0,0,I/O,TRUE,A,1,3
+A4,IO_L31P_0,0,I/O,TRUE,A,1,4
+A5,IO_L28N_0,0,I/O,TRUE,A,1,5
+A6,IO_L26N_0,0,I/O,TRUE,A,1,6
+A7,IO_L26P_0,0,I/O,TRUE,A,1,7
+A8,IO_L22N_0,0,I/O,TRUE,A,1,8
+A9,IO_L22P_0,0,I/O,TRUE,A,1,9
+A10,IO_L21P_0,0,I/O,TRUE,A,1,10
+A11,IO_L18N_0/GCLK7,0,GCLK,TRUE,A,1,11
+A12,IO_L18P_0/GCLK6,0,GCLK,TRUE,A,1,12
+A13,IO_L16N_0,0,I/O,TRUE,A,1,13
+A14,IO_L13N_0,0,I/O,TRUE,A,1,14
+A15,IO_L12N_0/VREF_0,0,VREF,TRUE,A,1,15
+A16,IO_L12P_0,0,I/O,TRUE,A,1,16
+A17,IO_L10N_0,0,I/O,TRUE,A,1,17
+A18,IO_L05N_0,0,I/O,TRUE,A,1,18
+A19,IO_L06N_0,0,I/O,TRUE,A,1,19
+A20,IO_L03N_0,0,I/O,TRUE,A,1,20
+A21,TCK,VCCAUX,JTAG,,A,1,21
+A22,GND,GND,GND,,A,1,22
+B1,IO_L02P_3,3,I/O,TRUE,B,2,1
+B2,IO_L36P_0/VREF_0,0,VREF,TRUE,B,2,2
+B3,IO_L33N_0,0,I/O,TRUE,B,2,3
+B4,IO_L31N_0,0,I/O,TRUE,B,2,4
+B5,VCCO_0,0,VCCO,,B,2,5
+B6,IO_L28P_0,0,I/O,TRUE,B,2,6
+B7,GND,GND,GND,,B,2,7
+B8,IO_L25P_0,0,I/O,TRUE,B,2,8
+B9,IO_L24P_0,0,I/O,TRUE,B,2,9
+B10,VCCO_0,0,VCCO,,B,2,10
+B11,IO_L19P_0/GCLK8,0,GCLK,TRUE,B,2,11
+B12,GND,GND,GND,,B,2,12
+B13,IO_L16P_0,0,I/O,TRUE,B,2,13
+B14,VCCO_0,0,VCCO,,B,2,14
+B15,IO_L13P_0,0,I/O,TRUE,B,2,15
+B16,GND,GND,GND,,B,2,16
+B17,IO_L10P_0,0,I/O,TRUE,B,2,17
+B18,VCCO_0,0,VCCO,,B,2,18
+B19,IO_L06P_0/VREF_0,0,VREF,TRUE,B,2,19
+B20,IO_L03P_0,0,I/O,TRUE,B,2,20
+B21,IO_L45N_1/A23,1,DUAL,TRUE,B,2,21
+B22,IO_L45P_1/A22,1,DUAL,TRUE,B,2,22
+C1,IO_L01P_3,3,I/O,TRUE,C,3,1
+C2,IO_L02N_3,3,I/O,TRUE,C,3,2
+C3,GND,GND,GND,,C,3,3
+C4,PROG_B,VCCAUX,CONFIG,,C,3,4
+C5,IO_L32P_0,0,I/O,TRUE,C,3,5
+C6,IO_L29P_0,0,I/O,TRUE,C,3,6
+C7,IO_L27N_0,0,I/O,TRUE,C,3,7
+C8,IO_L25N_0,0,I/O,TRUE,C,3,8
+C9,IO_L24N_0/VREF_0,0,VREF,TRUE,C,3,9
+C10,IO_L21N_0,0,I/O,TRUE,C,3,10
+C11,IO_L19N_0/GCLK9,0,GCLK,TRUE,C,3,11
+C12,IO_L17P_0/GCLK4,0,GCLK,TRUE,C,3,12
+C13,IO_L15N_0,0,I/O,TRUE,C,3,13
+C14,IO_L09P_0,0,I/O,TRUE,C,3,14
+C15,IO_L11N_0,0,I/O,TRUE,C,3,15
+C16,IO_L08N_0,0,I/O,TRUE,C,3,16
+C17,IO_L07N_0,0,I/O,TRUE,C,3,17
+C18,IO_L05P_0,0,I/O,TRUE,C,3,18
+C19,IO_L02N_0,0,I/O,TRUE,C,3,19
+C20,GND,GND,GND,,C,3,20
+C21,IO_L44N_1/A21,1,DUAL,TRUE,C,3,21
+C22,IO_L44P_1/A20,1,DUAL,TRUE,C,3,22
+D1,IO_L06P_3,3,I/O,TRUE,D,4,1
+D2,IO_L01N_3,3,I/O,TRUE,D,4,2
+D3,IO_L03P_3,3,I/O,TRUE,D,4,3
+D4,TMS,VCCAUX,JTAG,,D,4,4
+D5,IO_L32N_0,0,I/O,TRUE,D,4,5
+D6,IO_L29N_0,0,I/O,TRUE,D,4,6
+D7,IO_L27P_0,0,I/O,TRUE,D,4,7
+D8,IO_L30N_0,0,I/O,TRUE,D,4,8
+D9,GND,GND,GND,,D,4,9
+D10,IO_L23P_0,0,I/O,TRUE,D,4,10
+D11,IO_L20P_0/GCLK10,0,GCLK,TRUE,D,4,11
+D12,VCCAUX,VCCAUX,VCCAUX,,D,4,12
+D13,IO_L15P_0,0,I/O,TRUE,D,4,13
+D14,GND,GND,GND,,D,4,14
+D15,IO_L11P_0,0,I/O,TRUE,D,4,15
+D16,IO_L08P_0,0,I/O,TRUE,D,4,16
+D17,IO_L07P_0,0,I/O,TRUE,D,4,17
+D18,IO_L01N_0,0,I/O,TRUE,D,4,18
+D19,IO_L02P_0/VREF_0,0,VREF,TRUE,D,4,19
+D20,IO_L42N_1,1,I/O,TRUE,D,4,20
+D21,IO_L42P_1,1,I/O,TRUE,D,4,21
+D22,IO_L41N_1,1,I/O,TRUE,D,4,22
+E1,IO_L06N_3,3,I/O,TRUE,E,5,1
+E2,VCCO_3,3,VCCO,,E,5,2
+E3,IO_L07N_3,3,I/O,TRUE,E,5,3
+E4,IO_L03N_3,3,I/O,TRUE,E,5,4
+E5,VCCAUX,VCCAUX,VCCAUX,,E,5,5
+E6,IO_L35N_0,0,I/O,TRUE,E,5,6
+E7,IO_L34P_0,0,I/O,TRUE,E,5,7
+E8,IP_0,0,INPUT,,E,5,8
+E9,IO_L30P_0,0,I/O,TRUE,E,5,9
+E10,IO_L23N_0,0,I/O,TRUE,E,5,10
+E11,IO_L20N_0/GCLK11,0,GCLK,TRUE,E,5,11
+E12,IO_L17N_0/GCLK5,0,GCLK,TRUE,E,5,12
+E13,IO_L14N_0,0,I/O,TRUE,E,5,13
+E14,IO_L09N_0,0,I/O,TRUE,E,5,14
+E15,IO_L04P_0,0,I/O,TRUE,E,5,15
+E16,IP_0,0,INPUT,,E,5,16
+E17,IO_L01P_0,0,I/O,TRUE,E,5,17
+E18,VCCAUX,VCCAUX,VCCAUX,,E,5,18
+E19,TDO,VCCAUX,JTAG,,E,5,19
+E20,IO_L38P_1,1,I/O,TRUE,E,5,20
+E21,VCCO_1,1,VCCO,,E,5,21
+E22,IO_L41P_1,1,I/O,TRUE,E,5,22
+F1,IO_L12N_3,3,I/O,TRUE,F,6,1
+F2,IO_L12P_3,3,I/O,TRUE,F,6,2
+F3,IO_L08P_3,3,I/O,TRUE,F,6,3
+F4,IO_L07P_3,3,I/O,TRUE,F,6,4
+F5,TDI,VCCAUX,JTAG,,F,6,5
+F6,GND,GND,GND,,F,6,6
+F7,IO_L35P_0,0,I/O,TRUE,F,6,7
+F8,IO_L34N_0,0,I/O,TRUE,F,6,8
+F9,VCCO_0,0,VCCO,,F,6,9
+F10,IP_0,0,INPUT,,F,6,10
+F11,GND,GND,GND,,F,6,11
+F12,IP_0,0,INPUT,,F,6,12
+F13,IO_L14P_0,0,I/O,TRUE,F,6,13
+F14,VCCO_0,0,VCCO,,F,6,14
+F15,IO_L04N_0,0,I/O,TRUE,F,6,15
+F16,IP_0,0,INPUT,,F,6,16
+F17,GND,GND,GND,,F,6,17
+F18,IO_L40N_1,1,I/O,TRUE,F,6,18
+F19,IO_L40P_1,1,I/O,TRUE,F,6,19
+F20,IO_L38N_1,1,I/O,TRUE,F,6,20
+F21,IO_L34N_1/A19,1,DUAL,TRUE,F,6,21
+F22,IO_L34P_1/A18,1,DUAL,TRUE,F,6,22
+G1,IO_L13N_3,3,I/O,TRUE,G,7,1
+G2,GND,GND,GND,,G,7,2
+G3,IO_L13P_3,3,I/O,TRUE,G,7,3
+G4,IO_L08N_3,3,I/O,TRUE,G,7,4
+G5,IO_L05N_3,3,I/O,TRUE,G,7,5
+G6,IO_L05P_3,3,I/O,TRUE,G,7,6
+G7,IP_0,0,INPUT,,G,7,7
+G8,IP_0/VREF_0,0,VREF,,G,7,8
+G9,IP_0,0,INPUT,,G,7,9
+G10,IP_0,0,INPUT,,G,7,10
+G11,IP_0,0,INPUT,,G,7,11
+G12,IP_0,0,INPUT,,G,7,12
+G13,IP_0,0,INPUT,,G,7,13
+G14,IP_0,0,INPUT,,G,7,14
+G15,IP_0,0,INPUT,,G,7,15
+G16,IP_0,0,INPUT,,G,7,16
+G17,IO_L46N_1/A25,1,DUAL,TRUE,G,7,17
+G18,IO_L46P_1/A24,1,DUAL,TRUE,G,7,18
+G19,IO_L36P_1,1,I/O,TRUE,G,7,19
+G20,IO_L36N_1,1,I/O,TRUE,G,7,20
+G21,GND,GND,GND,,G,7,21
+G22,IO_L30N_1/A15,1,DUAL,TRUE,G,7,22
+H1,IO_L16N_3,3,I/O,TRUE,H,8,1
+H2,IO_L16P_3,3,I/O,TRUE,H,8,2
+H3,IO_L14N_3,3,I/O,TRUE,H,8,3
+H4,IO_L14P_3,3,I/O,TRUE,H,8,4
+H5,IO_L09P_3,3,I/O,TRUE,H,8,5
+H6,IO_L09N_3,3,I/O,TRUE,H,8,6
+H7,IP_L04N_3/VREF_3,3,VREF,TRUE,H,8,7
+H8,IP_L04P_3,3,INPUT,TRUE,H,8,8
+H9,IP_0/VREF_0,0,VREF,,H,8,9
+H10,IP_0,0,INPUT,,H,8,10
+H11,VCCAUX,VCCAUX,VCCAUX,,H,8,11
+H12,IP_0/VREF_0,0,VREF,,H,8,12
+H13,IP_0,0,INPUT,,H,8,13
+H14,IP_0,0,INPUT,,H,8,14
+H15,IP_L47N_1,1,INPUT,TRUE,H,8,15
+H16,IP_L47P_1/VREF_1,1,VREF,TRUE,H,8,16
+H17,IP_L39P_1,1,INPUT,TRUE,H,8,17
+H18,IP_L39N_1,1,INPUT,TRUE,H,8,18
+H19,IO_L37N_1,1,I/O,TRUE,H,8,19
+H20,IO_L33N_1/A17,1,DUAL,TRUE,H,8,20
+H21,IO_L33P_1/A16,1,DUAL,TRUE,H,8,21
+H22,IO_L30P_1/A14,1,DUAL,TRUE,H,8,22
+J1,IO_L17N_3/VREF_3,3,VREF,TRUE,J,9,1
+J2,VCCO_3,3,VCCO,,J,9,2
+J3,IO_L17P_3,3,I/O,TRUE,J,9,3
+J4,GND,GND,GND,,J,9,4
+J5,IO_L10N_3,3,I/O,TRUE,J,9,5
+J6,VCCO_3,3,VCCO,,J,9,6
+J7,IP_L11P_3,3,INPUT,TRUE,J,9,7
+J8,IP_3/VREF_3,3,VREF,,J,9,8
+J9,GND,GND,GND,,J,9,9
+J10,VCCINT,VCCINT,VCCINT,,J,9,10
+J11,GND,GND,GND,,J,9,11
+J12,VCCINT,VCCINT,VCCINT,,J,9,12
+J13,GND,GND,GND,,J,9,13
+J14,GND,GND,GND,,J,9,14
+J15,IP_L43N_1/VREF_1,1,VREF,TRUE,J,9,15
+J16,IP_L43P_1,1,INPUT,TRUE,J,9,16
+J17,VCCO_1,1,VCCO,,J,9,17
+J18,IO_L37P_1,1,I/O,TRUE,J,9,18
+J19,GND,GND,GND,,J,9,19
+J20,IO_L29N_1/A13,1,DUAL,TRUE,J,9,20
+J21,IO_L29P_1/A12,1,DUAL,TRUE,J,9,21
+J22,IO_L26N_1/A11,1,DUAL,TRUE,J,9,22
+K1,IO_L22P_3/LHCLK2,3,LHCLK,TRUE,K,10,1
+K2,IO_L20N_3,3,I/O,TRUE,K,10,2
+K3,IO_L20P_3,3,I/O,TRUE,K,10,3
+K4,IO_L18N_3,3,I/O,TRUE,K,10,4
+K5,IO_L18P_3,3,I/O,TRUE,K,10,5
+K6,IO_L10P_3,3,I/O,TRUE,K,10,6
+K7,IP_L15P_3,3,INPUT,TRUE,K,10,7
+K8,IP_L11N_3,3,INPUT,TRUE,K,10,8
+K9,VCCINT,VCCINT,VCCINT,,K,10,9
+K10,GND,GND,GND,,K,10,10
+K11,VCCINT,VCCINT,VCCINT,,K,10,11
+K12,GND,GND,GND,,K,10,12
+K13,VCCINT,VCCINT,VCCINT,,K,10,13
+K14,IP_L35P_1/VREF_1,1,VREF,TRUE,K,10,14
+K15,IP_L35N_1,1,INPUT,TRUE,K,10,15
+K16,IP_L31N_1,1,INPUT,TRUE,K,10,16
+K17,IO_L32P_1,1,I/O,TRUE,K,10,17
+K18,IO_L32N_1,1,I/O,TRUE,K,10,18
+K19,IO_L25N_1/RHCLK7,1,RHCLK,TRUE,K,10,19
+K20,IO_L25P_1/IRDY1/RHCLK6,1,RHCLK,TRUE,K,10,20
+K21,VCCO_1,1,VCCO,,K,10,21
+K22,IO_L26P_1/A10,1,DUAL,TRUE,K,10,22
+L1,IO_L22N_3/IRDY2/LHCLK3,3,LHCLK,TRUE,L,11,1
+L2,GND,GND,GND,,L,11,2
+L3,IO_L21N_3/LHCLK1,3,LHCLK,TRUE,L,11,3
+L4,VCCAUX,VCCAUX,VCCAUX,,L,11,4
+L5,IO_L21P_3/LHCLK0,3,LHCLK,TRUE,L,11,5
+L6,GND,GND,GND,,L,11,6
+L7,IP_L19P_3,3,INPUT,TRUE,L,11,7
+L8,IP_L15N_3/VREF_3,3,VREF,TRUE,L,11,8
+L9,GND,GND,GND,,L,11,9
+L10,VCCINT,VCCINT,VCCINT,,L,11,10
+L11,GND,GND,GND,,L,11,11
+L12,VCCINT,VCCINT,VCCINT,,L,11,12
+L13,GND,GND,GND,,L,11,13
+L14,VCCINT,VCCINT,VCCINT,,L,11,14
+L15,IP_L31P_1,1,INPUT,TRUE,L,11,15
+L16,IP_L27N_1,1,INPUT,TRUE,L,11,16
+L17,GND,GND,GND,,L,11,17
+L18,IO_L28P_1,1,I/O,TRUE,L,11,18
+L19,IO_L28N_1,1,I/O,TRUE,L,11,19
+L20,IO_L22N_1/TRDY1/RHCLK3,1,RHCLK,TRUE,L,11,20
+L21,IO_L22P_1/RHCLK2,1,RHCLK,TRUE,L,11,21
+L22,IO_L21N_1/RHCLK1,1,RHCLK,TRUE,L,11,22
+M1,IO_L24P_3/LHCLK4,3,LHCLK,TRUE,M,12,1
+M2,IO_L24N_3/LHCLK5,3,LHCLK,TRUE,M,12,2
+M3,IO_L25P_3/TRDY2/LHCLK6,3,LHCLK,TRUE,M,12,3
+M4,IO_L25N_3/LHCLK7,3,LHCLK,TRUE,M,12,4
+M5,IO_L30P_3,3,I/O,TRUE,M,12,5
+M6,IP_L23N_3,3,INPUT,TRUE,M,12,6
+M7,IP_L23P_3,3,INPUT,TRUE,M,12,7
+M8,IP_L19N_3,3,INPUT,TRUE,M,12,8
+M9,VCCINT,VCCINT,VCCINT,,M,12,9
+M10,GND,GND,GND,,M,12,10
+M11,VCCINT,VCCINT,VCCINT,,M,12,11
+M12,GND,GND,GND,,M,12,12
+M13,VCCINT,VCCINT,VCCINT,,M,12,13
+M14,GND,GND,GND,,M,12,14
+M15,IP_L27P_1/VREF_1,1,VREF,TRUE,M,12,15
+M16,IP_L23N_1,1,INPUT,TRUE,M,12,16
+M17,IP_L23P_1,1,INPUT,TRUE,M,12,17
+M18,IO_L24P_1/RHCLK4,1,RHCLK,TRUE,M,12,18
+M19,VCCAUX,VCCAUX,VCCAUX,,M,12,19
+M20,IO_L24N_1/RHCLK5,1,RHCLK,TRUE,M,12,20
+M21,GND,GND,GND,,M,12,21
+M22,IO_L21P_1/RHCLK0,1,RHCLK,TRUE,M,12,22
+N1,IO_L26P_3/VREF_3,3,VREF,TRUE,N,13,1
+N2,VCCO_3,3,VCCO,,N,13,2
+N3,IO_L26N_3,3,I/O,TRUE,N,13,3
+N4,IO_L30N_3,3,I/O,TRUE,N,13,4
+N5,IP_L31N_3,3,INPUT,TRUE,N,13,5
+N6,IP_L31P_3,3,INPUT,TRUE,N,13,6
+N7,IP_L35P_3,3,INPUT,TRUE,N,13,7
+N8,IP_L27P_3,3,INPUT,TRUE,N,13,8
+N9,IP_L27N_3,3,INPUT,TRUE,N,13,9
+N10,VCCINT,VCCINT,VCCINT,,N,13,10
+N11,GND,GND,GND,,N,13,11
+N12,VCCINT,VCCINT,VCCINT,,N,13,12
+N13,GND,GND,GND,,N,13,13
+N14,VCCINT,VCCINT,VCCINT,,N,13,14
+N15,IP_L16P_1,1,INPUT,TRUE,N,13,15
+N16,IP_L16N_1/VREF_1,1,VREF,TRUE,N,13,16
+N17,IO_L20N_1/A9,1,DUAL,TRUE,N,13,17
+N18,IO_L20P_1/A8,1,DUAL,TRUE,N,13,18
+N19,IO_L19N_1/A7,1,DUAL,TRUE,N,13,19
+N20,IO_L19P_1/A6,1,DUAL,TRUE,N,13,20
+N21,IO_L18N_1/A5,1,DUAL,TRUE,N,13,21
+N22,IO_L18P_1/A4,1,DUAL,TRUE,N,13,22
+P1,IO_L28P_3,3,I/O,TRUE,P,14,1
+P2,IO_L28N_3,3,I/O,TRUE,P,14,2
+P3,IO_L29P_3,3,I/O,TRUE,P,14,3
+P4,GND,GND,GND,,P,14,4
+P5,IO_L29N_3,3,I/O,TRUE,P,14,5
+P6,VCCO_3,3,VCCO,,P,14,6
+P7,IP_L39P_3,3,INPUT,TRUE,P,14,7
+P8,IP_L35N_3,3,INPUT,TRUE,P,14,8
+P9,GND,GND,GND,,P,14,9
+P10,GND,GND,GND,,P,14,10
+P11,VCCAUX,VCCAUX,VCCAUX,,P,14,11
+P12,IP_2,2,INPUT,,P,14,12
+P13,VCCINT,VCCINT,VCCINT,,P,14,13
+P14,GND,GND,GND,,P,14,14
+P15,IP_L08P_1,1,INPUT,TRUE,P,14,15
+P16,IP_L08N_1,1,INPUT,TRUE,P,14,16
+P17,VCCO_1,1,VCCO,,P,14,17
+P18,IO_L17N_1/A3,1,DUAL,TRUE,P,14,18
+P19,GND,GND,GND,,P,14,19
+P20,IO_L15P_1,1,I/O,TRUE,P,14,20
+P21,VCCO_1,1,VCCO,,P,14,21
+P22,IO_L15N_1/VREF_1,1,VREF,TRUE,P,14,22
+R1,IO_L32P_3,3,I/O,TRUE,R,15,1
+R2,IO_L32N_3,3,I/O,TRUE,R,15,2
+R3,IO_L33P_3,3,I/O,TRUE,R,15,3
+R4,IO_L33N_3,3,I/O,TRUE,R,15,4
+R5,IO_L34P_3,3,I/O,TRUE,R,15,5
+R6,IP_3/VREF_3,3,VREF,,R,15,6
+R7,IP_L46P_3,3,INPUT,TRUE,R,15,7
+R8,IP_L39N_3,3,INPUT,TRUE,R,15,8
+R9,IP_2,2,INPUT,,R,15,9
+R10,IP_2,2,INPUT,,R,15,10
+R11,IP_2,2,INPUT,,R,15,11
+R12,IP_2/VREF_2,2,VREF,,R,15,12
+R13,IP_2/VREF_2,2,VREF,,R,15,13
+R14,IP_2/VREF_2,2,VREF,,R,15,14
+R15,IP_L04P_1,1,INPUT,TRUE,R,15,15
+R16,IP_L04N_1/VREF_1,1,VREF,TRUE,R,15,16
+R17,IP_L12P_1,1,INPUT,TRUE,R,15,17
+R18,IP_L12N_1/VREF_1,1,VREF,TRUE,R,15,18
+R19,IO_L17P_1/A2,1,DUAL,TRUE,R,15,19
+R20,IO_L13P_1,1,I/O,TRUE,R,15,20
+R21,IO_L14P_1,1,I/O,TRUE,R,15,21
+R22,IO_L14N_1,1,I/O,TRUE,R,15,22
+T1,IO_L36P_3/VREF_3,3,VREF,TRUE,T,16,1
+T2,GND,GND,GND,,T,16,2
+T3,IO_L36N_3,3,I/O,TRUE,T,16,3
+T4,IO_L34N_3,3,I/O,TRUE,T,16,4
+T5,IO_L40P_3,3,I/O,TRUE,T,16,5
+T6,IP_L46N_3/VREF_3,3,VREF,TRUE,T,16,6
+T7,IP_2/VREF_2,2,VREF,,T,16,7
+T8,IP_2/VREF_2,2,VREF,,T,16,8
+T9,IP_2,2,INPUT,,T,16,9
+T10,IP_2/VREF_2,2,VREF,,T,16,10
+T11,IP_2/VREF_2,2,VREF,,T,16,11
+T12,GND,GND,GND,,T,16,12
+T13,IP_2,2,INPUT,,T,16,13
+T14,IP_2,2,INPUT,,T,16,14
+T15,IP_2/VREF_2,2,VREF,,T,16,15
+T16,IP_2/VREF_2,2,VREF,,T,16,16
+T17,IO_L03P_1/A0,1,DUAL,TRUE,T,16,17
+T18,IO_L03N_1/A1,1,DUAL,TRUE,T,16,18
+T19,IO_L13N_1,1,I/O,TRUE,T,16,19
+T20,IO_L11P_1,1,I/O,TRUE,T,16,20
+T21,GND,GND,GND,,T,16,21
+T22,IO_L11N_1,1,I/O,TRUE,T,16,22
+U1,IO_L37P_3,3,I/O,TRUE,U,17,1
+U2,IO_L37N_3,3,I/O,TRUE,U,17,2
+U3,IO_L41P_3,3,I/O,TRUE,U,17,3
+U4,IO_L41N_3,3,I/O,TRUE,U,17,4
+U5,IO_L40N_3,3,I/O,TRUE,U,17,5
+U6,GND,GND,GND,,U,17,6
+U7,IP_2,2,INPUT,,U,17,7
+U8,IP_2,2,INPUT,,U,17,8
+U9,VCCO_2,2,VCCO,,U,17,9
+U10,IP_2,2,INPUT,,U,17,10
+U11,IO_L17P_2/GCLK12,2,GCLK,TRUE,U,17,11
+U12,IO_L20N_2/GCLK3,2,GCLK,TRUE,U,17,12
+U13,IO_L26N_2/D3,2,DUAL,TRUE,U,17,13
+U14,VCCO_2,2,VCCO,,U,17,14
+U15,IP_2,2,INPUT,,U,17,15
+U16,IP_2,2,INPUT,,U,17,16
+U17,GND,GND,GND,,U,17,17
+U18,SUSPEND,VCCAUX,PWRMGMT,,U,17,18
+U19,IO_L10N_1,1,I/O,TRUE,U,17,19
+U20,IO_L10P_1,1,I/O,TRUE,U,17,20
+U21,IO_L09N_1,1,I/O,TRUE,U,17,21
+U22,IO_L09P_1,1,I/O,TRUE,U,17,22
+V1,IO_L38P_3,3,I/O,TRUE,V,18,1
+V2,VCCO_3,3,VCCO,,V,18,2
+V3,IO_L38N_3,3,I/O,TRUE,V,18,3
+V4,IO_L43P_3,3,I/O,TRUE,V,18,4
+V5,VCCAUX,VCCAUX,VCCAUX,,V,18,5
+V6,IO_L01P_2/M1,2,DUAL,TRUE,V,18,6
+V7,IP_2,2,INPUT,,V,18,7
+V8,IP_2/VREF_2,2,VREF,,V,18,8
+V9,IO_L09P_2/RDWR_B,2,DUAL,TRUE,V,18,9
+V10,IO_L13P_2,2,I/O,TRUE,V,18,10
+V11,IO_L17N_2/GCLK13,2,GCLK,TRUE,V,18,11
+V12,IO_L20P_2/GCLK2,2,GCLK,TRUE,V,18,12
+V13,IO_L26P_2/INIT_B,2,DUAL,TRUE,V,18,13
+V14,IO_L30P_2,2,I/O,TRUE,V,18,14
+V15,IO_L30N_2,2,I/O,TRUE,V,18,15
+V16,IO_L31N_2,2,I/O,TRUE,V,18,16
+V17,IO_L33N_2,2,I/O,TRUE,V,18,17
+V18,VCCAUX,VCCAUX,VCCAUX,,V,18,18
+V19,IO_L06P_1,1,I/O,TRUE,V,18,19
+V20,IO_L06N_1,1,I/O,TRUE,V,18,20
+V21,VCCO_1,1,VCCO,,V,18,21
+V22,IO_L07N_1,1,I/O,TRUE,V,18,22
+W1,IO_L42P_3,3,I/O,TRUE,W,19,1
+W2,IO_L42N_3,3,I/O,TRUE,W,19,2
+W3,IO_L43N_3,3,I/O,TRUE,W,19,3
+W4,IO_L02P_2/M2,2,DUAL,TRUE,W,19,4
+W5,IO_L01N_2/M0,2,DUAL,TRUE,W,19,5
+W6,IO_L05P_2,2,I/O,TRUE,W,19,6
+W7,IO_L07P_2,2,I/O,TRUE,W,19,7
+W8,IO_L11P_2/VS1,2,DUAL,TRUE,W,19,8
+W9,IO_L09N_2/VS2,2,DUAL,TRUE,W,19,9
+W10,GND,GND,GND,,W,19,10
+W11,VCCAUX,VCCAUX,VCCAUX,,W,19,11
+W12,IO_L18P_2/GCLK14,2,GCLK,TRUE,W,19,12
+W13,IO_L23P_2,2,I/O,TRUE,W,19,13
+W14,GND,GND,GND,,W,19,14
+W15,IO_L25P_2,2,I/O,TRUE,W,19,15
+W16,IO_L31P_2,2,I/O,TRUE,W,19,16
+W17,IO_L34N_2,2,I/O,TRUE,W,19,17
+W18,IO_L33P_2,2,I/O,TRUE,W,19,18
+W19,IO_L02P_1/LDC1,1,DUAL,TRUE,W,19,19
+W20,IO_L02N_1/LDC0,1,DUAL,TRUE,W,19,20
+W21,IO_L05N_1,1,I/O,TRUE,W,19,21
+W22,IO_L07P_1,1,I/O,TRUE,W,19,22
+Y1,IO_L44P_3,3,I/O,TRUE,Y,20,1
+Y2,IO_L44N_3,3,I/O,TRUE,Y,20,2
+Y3,GND,GND,GND,,Y,20,3
+Y4,IO_L02N_2/CSO_B,2,DUAL,TRUE,Y,20,4
+Y5,IO_L05N_2,2,I/O,TRUE,Y,20,5
+Y6,IO_L07N_2,2,I/O,TRUE,Y,20,6
+Y7,IO_L10P_2,2,I/O,TRUE,Y,20,7
+Y8,IO_L11N_2/VS0,2,DUAL,TRUE,Y,20,8
+Y9,IO_L14P_2/D7,2,DUAL,TRUE,Y,20,9
+Y10,IO_L13N_2,2,I/O,TRUE,Y,20,10
+Y11,IO_L16P_2/D5,2,DUAL,TRUE,Y,20,11
+Y12,IO_L18N_2/GCLK15,2,GCLK,TRUE,Y,20,12
+Y13,IO_L21N_2,2,I/O,TRUE,Y,20,13
+Y14,IO_L23N_2,2,I/O,TRUE,Y,20,14
+Y15,IO_L25N_2,2,I/O,TRUE,Y,20,15
+Y16,IO_L27N_2,2,I/O,TRUE,Y,20,16
+Y17,IO_L28N_2/D1,2,DUAL,TRUE,Y,20,17
+Y18,IO_L34P_2,2,I/O,TRUE,Y,20,18
+Y19,DONE,VCCAUX,CONFIG,,Y,20,19
+Y20,GND,GND,GND,,Y,20,20
+Y21,IO_L01N_1/LDC2,1,DUAL,TRUE,Y,20,21
+Y22,IO_L05P_1,1,I/O,TRUE,Y,20,22
+AA1,IO_L45P_3,3,I/O,TRUE,AA,21,1
+AA2,IO_L45N_3,3,I/O,TRUE,AA,21,2
+AA3,IO_L03N_2,2,I/O,TRUE,AA,21,3
+AA4,IO_L04N_2,2,I/O,TRUE,AA,21,4
+AA5,VCCO_2,2,VCCO,,AA,21,5
+AA6,IO_L08P_2,2,I/O,TRUE,AA,21,6
+AA7,GND,GND,GND,,AA,21,7
+AA8,IO_L12P_2,2,I/O,TRUE,AA,21,8
+AA9,VCCO_2,2,VCCO,,AA,21,9
+AA10,IO_L15P_2,2,I/O,TRUE,AA,21,10
+AA11,GND,GND,GND,,AA,21,11
+AA12,IO_L19P_2/GCLK0,2,GCLK,TRUE,AA,21,12
+AA13,VCCO_2,2,VCCO,,AA,21,13
+AA14,IO_L22P_2,2,I/O,TRUE,AA,21,14
+AA15,IO_L24N_2/DOUT,2,DUAL,TRUE,AA,21,15
+AA16,GND,GND,GND,,AA,21,16
+AA17,IO_L28P_2/D2,2,DUAL,TRUE,AA,21,17
+AA18,VCCO_2,2,VCCO,,AA,21,18
+AA19,IO_L32N_2,2,I/O,TRUE,AA,21,19
+AA20,IO_L36N_2/CCLK,2,DUAL,TRUE,AA,21,20
+AA21,IO_L35N_2,2,I/O,TRUE,AA,21,21
+AA22,IO_L01P_1/HDC,1,DUAL,TRUE,AA,21,22
+AB1,GND,GND,GND,,AB,22,1
+AB2,IO_L03P_2,2,I/O,TRUE,AB,22,2
+AB3,IO_L04P_2,2,I/O,TRUE,AB,22,3
+AB4,IO_L06P_2,2,I/O,TRUE,AB,22,4
+AB5,IO_L06N_2,2,I/O,TRUE,AB,22,5
+AB6,IO_L08N_2,2,I/O,TRUE,AB,22,6
+AB7,IO_L10N_2,2,I/O,TRUE,AB,22,7
+AB8,IO_L12N_2,2,I/O,TRUE,AB,22,8
+AB9,IO_L14N_2/D6,2,DUAL,TRUE,AB,22,9
+AB10,IO_L15N_2,2,I/O,TRUE,AB,22,10
+AB11,IO_L16N_2/D4,2,DUAL,TRUE,AB,22,11
+AB12,IO_L19N_2/GCLK1,2,GCLK,TRUE,AB,22,12
+AB13,IO_L21P_2,2,I/O,TRUE,AB,22,13
+AB14,IO_L22N_2/MOSI/CSI_B,2,DUAL,TRUE,AB,22,14
+AB15,IO_L24P_2/AWAKE,2,PWRMGMT,TRUE,AB,22,15
+AB16,IO_L27P_2,2,I/O,TRUE,AB,22,16
+AB17,IO_L29P_2,2,I/O,TRUE,AB,22,17
+AB18,IO_L29N_2,2,I/O,TRUE,AB,22,18
+AB19,IO_L32P_2,2,I/O,TRUE,AB,22,19
+AB20,IO_L36P_2/D0/DIN/MISO,2,DUAL,TRUE,AB,22,20
+AB21,IO_L35P_2,2,I/O,TRUE,AB,22,21
+AB22,GND,GND,GND,,AB,22,22
Copied: usrp-hw/trunk/sym/xilinx/xilinxgen-XC3S1400AFG484 (from rev 10570,
usrp-hw/trunk/sym/xilinx/xilinxgen256)
===================================================================
--- usrp-hw/trunk/sym/xilinx/xilinxgen-XC3S1400AFG484
(rev 0)
+++ usrp-hw/trunk/sym/xilinx/xilinxgen-XC3S1400AFG484 2009-03-07 01:10:14 UTC
(rev 10571)
@@ -0,0 +1,125 @@
+#!/usr/bin/python
+
+import re
+matchstr = re.compile("_")
+
+def writepin(file,number,name,linetype,pintype,pos):
+ #newname = matchstr.sub("\\_",name)
+ newname = name
+ file.write("%s\t\t%s\t%s\t%s\t\t%s\n" %
(number,pintype,linetype,pos,newname))
+
+pinfile = open ('XC3S1400AFG484.csv','r')
+
+boilerplate = '''
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3S1400AFG484-%s
+device=XC3S1400AFG484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A 1400 FG484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+'''
+
+configfile = open ('xc3s1400afg484-CFG.src', 'w')
+configfile.write(boilerplate % ("CFG",))
+
+jtagfile = open ('xc3s1400afg484-JTAG.src', 'w')
+jtagfile.write(boilerplate % ("JTAG",))
+powerfile = open ('xc3s1400afg484-PWR.src', 'w')
+powerfile.write(boilerplate % ("PWR",))
+topclockfile = open ('xc3s1400afg484-TOPCLK.src', 'w')
+topclockfile.write(boilerplate % ("TOPCLK",))
+botclockfile = open ('xc3s1400afg484-BOTCLK.src', 'w')
+botclockfile.write(boilerplate % ("BOTCLK",))
+lhclockfile = open ('xc3s1400afg484-LHCLK.src', 'w')
+lhclockfile.write(boilerplate % ("LHCLK",))
+rhclockfile = open ('xc3s1400afg484-RHCLK.src', 'w')
+rhclockfile.write(boilerplate % ("RHCLK",))
+
+iofiles = [0] * 4
+for i in range(4):
+ iofiles[i] = open ( ('xc3s1400afg484-IO%d.src' % (i,)), 'w')
+ iofiles[i].write(boilerplate % ('IO%d' % (i,),))
+
+dummy = pinfile.readline()
+lines = pinfile.readlines()
+
+for line in lines:
+ elements = line.strip().split(',')
+
+ pintype = elements[3]
+ #nc = elements[5] == "N.C."
+
+ #if(elements[5] != elements[9]) and not nc:
+ # print "error"
+ # print elements
+
+ #if nc and pintype != 'I/O' and pintype != 'VREF':
+ # print "error"
+ # print elements
+
+ if(pintype == 'GND'):
+ writepin(powerfile,elements[0],elements[1],'line','pwr','r')
+ elif(pintype == 'VCCAUX'):
+ writepin(powerfile,elements[0],elements[1],'line','pwr','l')
+ elif(pintype == 'VCCO'):
+ #writepin(powerfile,elements[3],elements[6],'line','pwr','l')
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','pwr','b')
+ elif(pintype == 'VCCINT'):
+ writepin(powerfile,elements[0],elements[1],'line','pwr','l')
+
+ elif(pintype == 'JTAG'):
+ writepin(jtagfile,elements[0],elements[1],'line','io','l')
+
+ elif(pintype == 'CONFIG'):
+ writepin(configfile,elements[0],elements[1],'line','io','b')
+
+ elif(pintype == 'PWRMGMT'):
+ writepin(configfile,elements[0],elements[1],'line','io','b')
+
+ elif(pintype == 'DUAL'):
+ if(int(elements[2]) == 1): # All these are for BPI mode, so just put
in bank 1
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','l')
+ elif(int(elements[2]) == 2):
+ writepin(configfile,elements[0],elements[1],'line','io','r')
+ else:
+ writepin(configfile,elements[0],elements[1],'line','io','l')
+
+ elif(pintype == 'GCLK'):
+ if(int(elements[2]) == 0):
+ writepin(topclockfile,elements[0],elements[1],'clk','clk','l')
+ else:
+ writepin(botclockfile,elements[0],elements[1],'clk','clk','l')
+
+ elif(pintype == 'LHCLK'):
+ writepin(lhclockfile,elements[0],elements[1],'clk','clk','l')
+
+ elif(pintype == 'RHCLK'):
+ writepin(rhclockfile,elements[0],elements[1],'clk','clk','l')
+
+ elif(pintype == 'VREF'):
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','r')
+
+ elif(pintype == 'I/O'):
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','l')
+
+ elif(pintype == 'INPUT'):
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','in','r')
+
+ elif(pintype == 'DCI'):
+ writepin(iofiles[int(elements[12])],elements[3],"%s/DCI" %
(elements[6],),'line','io','l')
+
+ else:
+ print elements
Copied: usrp-hw/trunk/sym/xilinx/xilinxgen-XC3S1400AFT256 (from rev 10570,
usrp-hw/trunk/sym/xilinx/xilinxgen256)
===================================================================
--- usrp-hw/trunk/sym/xilinx/xilinxgen-XC3S1400AFT256
(rev 0)
+++ usrp-hw/trunk/sym/xilinx/xilinxgen-XC3S1400AFT256 2009-03-07 01:10:14 UTC
(rev 10571)
@@ -0,0 +1,125 @@
+#!/usr/bin/python
+
+import re
+matchstr = re.compile("_")
+
+def writepin(file,number,name,linetype,pintype,pos):
+ #newname = matchstr.sub("\\_",name)
+ newname = name
+ file.write("%s\t\t%s\t%s\t%s\t\t%s\n" %
(number,pintype,linetype,pos,newname))
+
+pinfile = open ('XC3S1400AFT256.csv','r')
+
+boilerplate = '''
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3S1400AFT256-%s
+device=XC3S1400AFT256
+refdes=U?
+footprint=CS256
+description=Xilinx Spartan 3A 1400 FT256
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+'''
+
+configfile = open ('xc3s1400aft256-CFG.src', 'w')
+configfile.write(boilerplate % ("CFG",))
+
+jtagfile = open ('xc3s1400aft256-JTAG.src', 'w')
+jtagfile.write(boilerplate % ("JTAG",))
+powerfile = open ('xc3s1400aft256-PWR.src', 'w')
+powerfile.write(boilerplate % ("PWR",))
+topclockfile = open ('xc3s1400aft256-TOPCLK.src', 'w')
+topclockfile.write(boilerplate % ("TOPCLK",))
+botclockfile = open ('xc3s1400aft256-BOTCLK.src', 'w')
+botclockfile.write(boilerplate % ("BOTCLK",))
+lhclockfile = open ('xc3s1400aft256-LHCLK.src', 'w')
+lhclockfile.write(boilerplate % ("LHCLK",))
+rhclockfile = open ('xc3s1400aft256-RHCLK.src', 'w')
+rhclockfile.write(boilerplate % ("RHCLK",))
+
+iofiles = [0] * 4
+for i in range(4):
+ iofiles[i] = open ( ('xc3s1400aft256-IO%d.src' % (i,)), 'w')
+ iofiles[i].write(boilerplate % ('IO%d' % (i,),))
+
+dummy = pinfile.readline()
+lines = pinfile.readlines()
+
+for line in lines:
+ elements = line.strip().split(',')
+
+ pintype = elements[3]
+ #nc = elements[5] == "N.C."
+
+ #if(elements[5] != elements[9]) and not nc:
+ # print "error"
+ # print elements
+
+ #if nc and pintype != 'I/O' and pintype != 'VREF':
+ # print "error"
+ # print elements
+
+ if(pintype == 'GND'):
+ writepin(powerfile,elements[0],elements[2],'line','pwr','r')
+ elif(pintype == 'VCCAUX'):
+ writepin(powerfile,elements[0],elements[2],'line','pwr','l')
+ elif(pintype == 'VCCO'):
+ #writepin(powerfile,elements[3],elements[6],'line','pwr','l')
+
writepin(iofiles[int(elements[1])],elements[0],elements[2],'line','pwr','b')
+ elif(pintype == 'VCCINT'):
+ writepin(powerfile,elements[0],elements[2],'line','pwr','l')
+
+ elif(pintype == 'JTAG'):
+ writepin(jtagfile,elements[0],elements[2],'line','io','l')
+
+ elif(pintype == 'CONFIG'):
+ writepin(configfile,elements[0],elements[2],'line','io','b')
+
+ elif(pintype == 'PWRMGMT'):
+ writepin(configfile,elements[0],elements[2],'line','io','b')
+
+ elif(pintype == 'DUAL'):
+ if(int(elements[1]) == 1): # All these are for BPI mode, so just put
in bank 1
+
writepin(iofiles[int(elements[1])],elements[0],elements[2],'line','io','l')
+ elif(int(elements[1]) == 2):
+ writepin(configfile,elements[0],elements[2],'line','io','r')
+ else:
+ writepin(configfile,elements[0],elements[2],'line','io','l')
+
+ elif(pintype == 'GCLK'):
+ if(int(elements[1]) == 0):
+ writepin(topclockfile,elements[0],elements[2],'clk','clk','l')
+ else:
+ writepin(botclockfile,elements[0],elements[2],'clk','clk','l')
+
+ elif(pintype == 'LHCLK'):
+ writepin(lhclockfile,elements[0],elements[2],'clk','clk','l')
+
+ elif(pintype == 'RHCLK'):
+ writepin(rhclockfile,elements[0],elements[2],'clk','clk','l')
+
+ elif(pintype == 'VREF'):
+
writepin(iofiles[int(elements[1])],elements[0],elements[2],'line','io','r')
+
+ elif(pintype == 'I/O'):
+
writepin(iofiles[int(elements[1])],elements[0],elements[2],'line','io','l')
+
+ elif(pintype == 'INPUT'):
+
writepin(iofiles[int(elements[1])],elements[0],elements[2],'line','in','r')
+
+ elif(pintype == 'DCI'):
+ writepin(iofiles[int(elements[12])],elements[3],"%s/DCI" %
(elements[6],),'line','io','l')
+
+ else:
+ print elements
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