[Commit-gnuradio] r9779 - in gnuradio/trunk/usrp2: firmware/lib fpga/control_lib fpga/top/u2_core fpga/top/u2_rev3

[matt]

Author: matt
Date: 2008-10-11 17:04:06 -0600 (Sat, 11 Oct 2008)
New Revision: 9779

Modified:
   gnuradio/trunk/usrp2/firmware/lib/memory_map.h
   gnuradio/trunk/usrp2/fpga/control_lib/icache.v
   gnuradio/trunk/usrp2/fpga/control_lib/ram_harv_cache.v
   gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v
   gnuradio/trunk/usrp2/fpga/top/u2_rev3/Makefile
Log:
New serdes status interrupt, clk_status interrupt.  New capability to flush the 
ICache.


Modified: gnuradio/trunk/usrp2/firmware/lib/memory_map.h
===================================================================
--- gnuradio/trunk/usrp2/firmware/lib/memory_map.h      2008-10-11 23:02:50 UTC 
(rev 9778)
+++ gnuradio/trunk/usrp2/firmware/lib/memory_map.h      2008-10-11 23:04:06 UTC 
(rev 9779)
@@ -354,6 +354,7 @@
   volatile uint32_t    phy_ctrl;       // LSB is reset line to eth phy
   volatile uint32_t    debug_mux_ctrl;
   volatile uint32_t     ram_page;       // FIXME should go somewhere else...
+  volatile uint32_t     flush_icache;   // Flush the icache
 } output_regs_t;
 
 #define SERDES_ENABLE 8
@@ -482,6 +483,8 @@
 #define        IRQ_PPS         7       // pulse per second
 #define        IRQ_UART_RX     8
 #define        IRQ_UART_TX     9
+#define        IRQ_SERDES      10
+#define        IRQ_CLKSTATUS   11
 
 #define IRQ_TO_MASK(x) (1 << (x))
 
@@ -495,8 +498,9 @@
 #define PIC_PPS_INT      IRQ_TO_MASK(IRQ_PPS)
 #define PIC_UART_RX_INT   IRQ_TO_MASK(IRQ_UART_RX)
 #define PIC_UART_TX_INT   IRQ_TO_MASK(IRQ_UART_TX)
+#define PIC_SERDES        IRQ_TO_MASK(IRQ_SERDES)
+#define PIC_CLKSTATUS     IRQ_TO_MASK(IRQ_CLKSTATUS)
 
-
 typedef struct {
   volatile uint32_t edge_enable; // mask: 1 -> edge triggered, 0 -> level
   volatile uint32_t polarity;   // mask: 1 -> rising edge

Modified: gnuradio/trunk/usrp2/fpga/control_lib/icache.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/control_lib/icache.v      2008-10-11 23:02:50 UTC 
(rev 9778)
+++ gnuradio/trunk/usrp2/fpga/control_lib/icache.v      2008-10-11 23:04:06 UTC 
(rev 9779)
@@ -11,7 +11,8 @@
      output iwb_ack_o,
      input [31:0] iram_dat_i,
      output [AWIDTH-1:0] iram_adr_o,
-     output iram_en_o );
+     output iram_en_o,
+     input flush);
 
    localparam TAGWIDTH = AWIDTH-CWIDTH-2;
    reg               stb_d1, ack_d1, miss_d1;
@@ -28,7 +29,7 @@
    // Write into cache
    integer           i;
    always @(posedge wb_clk_i)
-     if(wb_rst_i)
+     if(wb_rst_i | flush)
        for(i=0;i<(1<<CWIDTH);i=i+1)
         ivalid[i] <= 0;
      else

Modified: gnuradio/trunk/usrp2/fpga/control_lib/ram_harv_cache.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/control_lib/ram_harv_cache.v      2008-10-11 
23:02:50 UTC (rev 9778)
+++ gnuradio/trunk/usrp2/fpga/control_lib/ram_harv_cache.v      2008-10-11 
23:04:06 UTC (rev 9779)
@@ -25,8 +25,10 @@
      input dwb_we_i,
      output dwb_ack_o,
      input dwb_stb_i,
-     input [3:0] dwb_sel_i );
+     input [3:0] dwb_sel_i,
 
+     input flush_icache );
+
    wire [31:0]          iram_dat, dram_dat_i, dram_dat_o;
    wire [AWIDTH-1:0] iram_adr, dram_adr;
    wire             iram_en, dram_en, dram_we;
@@ -60,7 +62,8 @@
      icache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i),
            .iwb_adr_i(iwb_adr_i),.iwb_stb_i(iwb_stb_i),
            .iwb_dat_o(iwb_dat_o),.iwb_ack_o(iwb_ack_o),
-           .iram_dat_i(iram_dat),.iram_adr_o(iram_adr),.iram_en_o(iram_en) );
+           .iram_dat_i(iram_dat),.iram_adr_o(iram_adr),.iram_en_o(iram_en),
+           .flush(flush_icache));
 
    // RAM loader
    assign       ram_loader_ack_o = ram_loader_stb_i;

Modified: gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v     2008-10-11 23:02:50 UTC 
(rev 9778)
+++ gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v     2008-10-11 23:04:06 UTC 
(rev 9779)
@@ -283,6 +283,7 @@
    // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
    // I-port connects directly to processor and ram loader
 
+   wire         flush_icache;
    ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
      sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
             
@@ -295,11 +296,15 @@
             .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
             
             .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), 
.dwb_dat_o(s0_dat_i),
-            .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), 
.dwb_sel_i(s0_sel));
+            .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), 
.dwb_sel_i(s0_sel),
+            .flush_icache(flush_icache));
    
    assign       s0_err = 1'b0;
    assign       s0_rty = 1'b0;
 
+   setting_reg #(.my_addr(7)) sr_icache 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+                                        
.in(set_data),.out(),.changed(flush_icache));
+
    // Buffer Pool, slave #1
    wire         rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop;
    wire         rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop;
@@ -388,7 +393,7 @@
       
       
.word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
       
.word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
-      
.word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10({30'b0,clk_func,clk_status}),
+      
.word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
       
.word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
       );
 
@@ -479,7 +484,7 @@
    // /////////////////////////////////////////////////////////////////////////
    // Interrupt Controller, Slave #8
 
-   wire [15:0]          irq={{5'b0, serdes_link_up, uart_tx_int, uart_rx_int},
+   wire [15:0]          irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, 
uart_rx_int},
                      
{pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
    
    simple_pic #(.is(16),.dwidth(32)) simple_pic

Modified: gnuradio/trunk/usrp2/fpga/top/u2_rev3/Makefile
===================================================================
--- gnuradio/trunk/usrp2/fpga/top/u2_rev3/Makefile      2008-10-11 23:02:50 UTC 
(rev 9778)
+++ gnuradio/trunk/usrp2/fpga/top/u2_rev3/Makefile      2008-10-11 23:04:06 UTC 
(rev 9779)
@@ -62,7 +62,6 @@
 control_lib/dcache.v \
 control_lib/decoder_3_8.v \
 control_lib/dpram32.v \
-control_lib/extram_interface.v \
 control_lib/fifo_2clock.v \
 control_lib/fifo_2clock_casc.v \
 control_lib/gray2bin.v \