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[Commit-gnuradio] r9105 - usrp2/trunk/fpga/top/u2_core
From: |
matt |
Subject: |
[Commit-gnuradio] r9105 - usrp2/trunk/fpga/top/u2_core |
Date: |
Thu, 31 Jul 2008 20:36:46 -0600 (MDT) |
Author: matt
Date: 2008-07-31 20:36:46 -0600 (Thu, 31 Jul 2008)
New Revision: 9105
Modified:
usrp2/trunk/fpga/top/u2_core/u2_core.v
Log:
fifo level information for debugging
Modified: usrp2/trunk/fpga/top/u2_core/u2_core.v
===================================================================
--- usrp2/trunk/fpga/top/u2_core/u2_core.v 2008-08-01 02:35:03 UTC (rev
9104)
+++ usrp2/trunk/fpga/top/u2_core/u2_core.v 2008-08-01 02:36:46 UTC (rev
9105)
@@ -67,6 +67,8 @@
input cpld_din,
input cpld_clk,
input cpld_detached,
+ //input por,
+ //output config_success,
// ADC
input [13:0] adc_a,
@@ -147,6 +149,11 @@
wire [31:0] debug_rx, debug_mac0, debug_mac1, debug_tx_dsp,
debug_txc,
debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp;
+
+ wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ,
eth_rx_occ, eth_tx_occ, eth_rx_occ2;
+ wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full,
eth_rx_full, eth_tx_full, eth_rx_full2;
+ wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty,
eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+
//
///////////////////////////////////////////////////////////////////////////////////////////////
// Wishbone Single Master INTERCON
parameter dw = 32; // Data bus width
@@ -208,10 +215,12 @@
//////////////////////////////////////////////////////////////////////////////////////////
// Reset Controller
- system_control sysctrl (.wb_clk_i(wb_clk),
+ system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
.ram_loader_rst_o(ram_loader_rst),
.wb_rst_o(wb_rst),
.ram_loader_done_i(ram_loader_done));
+
+ //assign config_success = ram_loader_done;
// ///////////////////////////////////////////////////////////////////
// RAM Loader
@@ -422,6 +431,8 @@
.Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),
.Crs(GMII_CRS),.Col(GMII_COL),
.Mdio(MDIO),.Mdc(MDC),
+
.rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2),
+ .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(),
.debug0(debug_mac0),.debug1(debug_mac1) );
assign s6_err = 1'b0;
@@ -433,15 +444,17 @@
.Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop),
.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
.wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done),
- .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full) );
+ .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full),
+
.fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) );
mac_txfifo_int mac_txfifo_int
(.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac),
.Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
.Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
.rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done),
- .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop) );
-
+ .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop),
+
.fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) );
+
// /////////////////////////////////////////////////////////////////////////
// Interrupt Controller, Slave #8
@@ -521,6 +534,7 @@
.wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done),
.wr_error_o(wr1_error),
.wr_ready_i(wr1_ready), .wr_full_i(wr1_full),
.sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+
.fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
.debug_rx(debug_rx) );
// dummy_rx dsp_core_rx
@@ -538,6 +552,7 @@
.rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop),
.rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error),
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+
.fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty),
.debug(debug_txc) );
dsp_core_tx dsp_core_tx
@@ -559,6 +574,8 @@
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
.wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error),
.wr_ready_i(wr0_ready),.wr_full_i(wr0_full),
+ .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
+ .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
.debug0(debug_serdes0), .debug1(debug_serdes1) );
//
///////////////////////////////////////////////////////////////////////////////////
@@ -578,6 +595,30 @@
//
/////////////////////////////////////////////////////////////////////////////////////////
// Debug Pins
+ // FIFO Level Debugging
+ reg [31:0] host_to_dsp_fifo, dsp_to_host_fifo, eth_mac_debug;
+
+ always @(posedge dsp_clk)
+ host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
+ {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+
+ always @(posedge dsp_clk)
+ dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
+ {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+
+ always @(posedge dsp_clk)
+ eth_mac_debug <= {
+ // {eth_tx_full2, eth_tx_empty2, eth_tx_occ2[13:0]},
+ // {underrun, overrun, debug_mac0[13:0] },
+ {debug_txc[15:0]},
+ {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
+
+ wire debug_mux;
+ setting_reg #(.my_addr(5)) sr_debug
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+
.in(set_data),.out(debug_mux),.changed());
+
+ assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
+
// Assign various commonly used debug buses.
/*
wire [31:0] debug_rx_1 =
{uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
@@ -625,13 +666,13 @@
assign debug_clk[0] = wb_clk;
assign debug_clk[1] = dsp_clk;
- assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
- {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
+ //assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
+ // {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
//assign debug = debug_tx_dsp;
+ //assign debug = debug_serdes0;
- //assign debug = 0; // debug_serdes0;
assign debug_gpio_0 = 0; // debug_serdes1;
- assign debug_gpio_1 = 32'b0;
+ assign debug_gpio_1 = eth_mac_debug;
endmodule // u2_core
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