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[Commit-gnuradio] r9099 - usrp2/trunk/fpga/eth/rtl/verilog
From: |
matt |
Subject: |
[Commit-gnuradio] r9099 - usrp2/trunk/fpga/eth/rtl/verilog |
Date: |
Thu, 31 Jul 2008 20:27:43 -0600 (MDT) |
Author: matt
Date: 2008-07-31 20:27:42 -0600 (Thu, 31 Jul 2008)
New Revision: 9099
Modified:
usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
Log:
pins for rx and tx fifo level outputs. Only rx fifo levels are hooked up.
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v 2008-08-01 02:26:42 UTC (rev
9098)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v 2008-08-01 02:27:42 UTC (rev
9099)
@@ -91,6 +91,14 @@
inout Mdio,
output Mdc,
+ // FIFO levels
+ output [15:0] rx_fifo_occupied,
+ output rx_fifo_full,
+ output rx_fifo_empty,
+ output [15:0] tx_fifo_occupied,
+ output tx_fifo_full,
+ output tx_fifo_empty,
+
// Debug Interface
output [31:0] debug0,
output [31:0] debug1
@@ -248,6 +256,10 @@
.Rx_apply_rmon ( Rx_apply_rmon ),
.Rx_pkt_err_type_rmon ( Rx_pkt_err_type_rmon ),
.Rx_pkt_type_rmon ( Rx_pkt_type_rmon ),
+
+ .rx_fifo_occupied(rx_fifo_occupied),
+ .rx_fifo_full(rx_fifo_full),
+ .rx_fifo_empty(rx_fifo_empty),
.debug(debug_rx)
);
@@ -495,9 +507,10 @@
.UpdateMIIRX_DATAReg ( UpdateMIIRX_DATAReg )
);
- assign debug0 = {{debug_rx[3:0], xon_gen, xon_gen_complete, xoff_gen,
xoff_gen_complete},
-
{1'b0,Rx_mac_err,Rx_mac_empty,Rx_mac_rd,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]},
- {rx_fifo_space}};
+ assign debug0 = {xon_gen, xoff_gen, Tx_en, Rx_dv};
+ //assign debug0 = {{debug_rx[3:0], xon_gen, xon_gen_complete, xoff_gen,
xoff_gen_complete},
+ //
{1'b0,Rx_mac_err,Rx_mac_empty,Rx_mac_rd,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]},
+ // {rx_fifo_space}};
//assign debug0 = debug_tx0;
//assign debug1 = debug_tx1;
endmodule
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- [Commit-gnuradio] r9099 - usrp2/trunk/fpga/eth/rtl/verilog,
matt <=