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[Commit-gnuradio] r8998 - gnuradio/branches/developers/gnychis/fpga/usrp
From: |
gnychis |
Subject: |
[Commit-gnuradio] r8998 - gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches |
Date: |
Thu, 24 Jul 2008 13:13:54 -0600 (MDT) |
Author: gnychis
Date: 2008-07-24 13:13:54 -0600 (Thu, 24 Jul 2008)
New Revision: 8998
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tb_timestamps.v
Log:
working on testbench for the timestamps
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tb_timestamps.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tb_timestamps.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tb_timestamps.v
2008-07-24 19:13:54 UTC (rev 8998)
@@ -0,0 +1,45 @@
+module tb_timestamps();
+
+ reg [31:0] timestamp_clock;
+ reg usbclk;
+ reg bus_reset;
+ reg reset;
+ reg reset_regs;
+ reg clock_reset;
+ wire [15:0] usbdata;
+ reg RD;
+ wire have_pkt_rdy;
+ wire rx_overrun;
+ reg [3:0] channels;
+ reg [15:0] ch_0;
+ reg [15:0] ch_1;
+ reg [15:0] ch_2;
+ reg [15:0] ch_3;
+ reg [15:0] ch_4;
+ reg [15:0] ch_5;
+ reg [15:0] ch_6;
+ reg [15:0] ch_7;
+ reg rxclk;
+ reg rxstrobe;
+ reg clear_status;
+ reg [6:0] serial_addr;
+ reg [31:0] serial_data;
+ reg serial_strobe;
+ wire [15:0] debugbus;
+
+ rx_buffer_inband rx_buffer
+ (.timestamp_clock(timestamp_clock), .usbclk(usbclk), .bus_reset(bus_reset),
+ .reset(reset), .reset_regs(reset_regs), .clock_reset(clock_reset),
.usbdata(usbdata),
+ .RD(RD), .have_pkt_rdy(have_pkt_rdy), .rx_overrun(rx_overrun),
.channels(channels),
+ .ch_0(ch_0), .ch_1(ch_1), .ch_2(ch_2), .ch_3(ch_3), .ch_4(ch_4),
.ch_5(ch_5), .ch_6(ch_6), .ch_7(ch_7),
+ .rxclk(rxclk), .rxstrobe(rxstrobe), .clear_status(clear_status),
.serial_addr(serial_addr),
+ .serial_strobe(serial_strobe), .debugbus(debugbus));
+
+ // I am not sure of this...
+ strobe_gen sgen
+ (.timestamp_clock(timestamp_clock), .reset(reset), .rxclk(rxclk),
.rxstrobe(rxstrobe));
+
+ always
+ #5 rxclk = ~rxclk;
+
+endmodule
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