[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r8987 - gnuradio/branches/developers/gnychis/fpga/usrp
From: |
gnychis |
Subject: |
[Commit-gnuradio] r8987 - gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb |
Date: |
Wed, 23 Jul 2008 17:45:23 -0600 (MDT) |
Author: gnychis
Date: 2008-07-23 17:45:22 -0600 (Wed, 23 Jul 2008)
New Revision: 8987
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
work in progress on a single clock as input to both TX and RX modules, rather
than two clocks reset at the same time
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2008-07-23 23:32:23 UTC (rev 8986)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2008-07-23 23:45:22 UTC (rev 8987)
@@ -113,8 +113,13 @@
reg [15:0] debug_counter;
reg [15:0] loopback_i_0,loopback_q_0;
-
+ // Single timestamp clock for both TX and RX
+ reg [31:0] timestamp_clock;
+ always @(posedge clk64) // reset the timestamp clock on TX DSP reset
+ if(tx_dsp_reset)
+ timestamp_clock <= #1 32'd0;
+
//Connection RX inband <-> TX inband
wire rx_WR;
wire [15:0] rx_databus;
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r8987 - gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb,
gnychis <=