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[Commit-gnuradio] r8908 - usrp2/trunk/fpga/control_lib
From: |
matt |
Subject: |
[Commit-gnuradio] r8908 - usrp2/trunk/fpga/control_lib |
Date: |
Wed, 16 Jul 2008 18:21:54 -0600 (MDT) |
Author: matt
Date: 2008-07-16 18:21:13 -0600 (Wed, 16 Jul 2008)
New Revision: 8908
Added:
usrp2/trunk/fpga/control_lib/oneshot_2clk.v
Log:
one shot for passing reset and other single-bit signals across clock domains
Added: usrp2/trunk/fpga/control_lib/oneshot_2clk.v
===================================================================
--- usrp2/trunk/fpga/control_lib/oneshot_2clk.v (rev 0)
+++ usrp2/trunk/fpga/control_lib/oneshot_2clk.v 2008-07-17 00:21:13 UTC (rev
8908)
@@ -0,0 +1,36 @@
+
+// Retime a single bit from one clock domain to another
+// Guarantees that no matter what the relative clock rates, if the in signal
is high for at least
+// one clock cycle in the clk_in domain, then the out signal will be high
for at least one
+// clock cycle in the clk_out domain. If the in signal goes high again
before the process is done
+// the behavior is undefined. No other guarantees. Designed for passing
reset into a new
+// clock domain.
+
+module oneshot_2clk
+ (input clk_in,
+ input in,
+ input clk_out,
+ output out);
+
+ reg [2:0] del_in = 0;
+ reg sendit_in = 0, gotit_in = 0, sendit_out = 0, gotit_out = 0;
+ reg sendit_d = 0, gotit_d = 0;
+
+ always @(posedge clk_in) del_in <= {del_in[1:0],in};
+
+ always @(posedge clk_in)
+ if(del_in[1] & ~del_in[2]) // we have a positive edge
+ sendit_in <= 1;
+ else if(gotit_in)
+ sendit_in <= 0;
+
+ always @(posedge clk_out) sendit_d <= sendit_in;
+ always @(posedge clk_out) sendit_out <= sendit_d;
+ always @(posedge clk_out) gotit_out <= sendit_out;
+
+ always @(posedge clk_in) gotit_d <= gotit_out;
+ always @(posedge clk_in) gotit_in <= gotit_d;
+
+endmodule // oneshot_2clk
+
+
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