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[Commit-gnuradio] r8889 - usrp2/trunk/fpga/top/u2_rev2
From: |
matt |
Subject: |
[Commit-gnuradio] r8889 - usrp2/trunk/fpga/top/u2_rev2 |
Date: |
Tue, 15 Jul 2008 15:02:01 -0600 (MDT) |
Author: matt
Date: 2008-07-15 15:01:55 -0600 (Tue, 15 Jul 2008)
New Revision: 8889
Modified:
usrp2/trunk/fpga/top/u2_rev2/Makefile
Log:
added new properties to mapping to get us to pass timing, also have a "quick"
option which produces a slow design quickly.
Modified: usrp2/trunk/fpga/top/u2_rev2/Makefile
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/Makefile 2008-07-15 02:47:17 UTC (rev
8888)
+++ usrp2/trunk/fpga/top/u2_rev2/Makefile 2008-07-15 21:01:55 UTC (rev
8889)
@@ -86,6 +86,7 @@
control_lib/simple_uart_tx.v \
control_lib/simple_uart_rx.v \
coregen/fifo_generator_v4_1.v \
+coregen/fifo_generator_v4_1.xco \
eth/mac_rxfifo_int.v \
eth/mac_txfifo_int.v \
eth/rtl/verilog/Clk_ctrl.v \
@@ -188,11 +189,22 @@
export TRANSLATE_PROPERTIES := \
"Macro Search Path" "$(SOURCE_ROOT)/coregen/"
+QUICK_MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
export MAP_PROPERTIES := \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Optimization Strategy (Cover Mode)" Speed \
-"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
export PLACE_ROUTE_PROPERTIES := \
"Place & Route Effort Level (Overall)" High
@@ -228,6 +240,9 @@
bin:
PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
+quick:
+ PROCESS_RUN="Generate Programming File"
MAP_PROPERTIES='$(QUICK_MAP_PROPERTIES)' $(XTCLSH) $(ISE_HELPER)
+
clean:
rm -rf $(BUILD_DIR)
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