[Commit-gnuradio] r8719 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2008-06-25 23:09:23 -0600 (Wed, 25 Jun 2008)
New Revision: 8719

Added:
   usrp2/trunk/fpga/control_lib/simple_uart_rx.v
Modified:
   usrp2/trunk/fpga/control_lib/simple_uart.v
   usrp2/trunk/fpga/control_lib/simple_uart_tx.v
Log:
Added longer fifos to the tx and redid the memory map.  Also added in the rx, 
which is only a shell for now


Modified: usrp2/trunk/fpga/control_lib/simple_uart.v
===================================================================
--- usrp2/trunk/fpga/control_lib/simple_uart.v  2008-06-26 05:07:11 UTC (rev 
8718)
+++ usrp2/trunk/fpga/control_lib/simple_uart.v  2008-06-26 05:09:23 UTC (rev 
8719)
@@ -1,25 +1,27 @@
 
 module simple_uart
-  (input clk_i, input rst_i,
-   input we_i, input stb_i, input cyc_i, output reg ack_o,
-   input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
-   output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
-
+  #(parameter TXDEPTH = 1,
+    parameter RXDEPTH = 1)
+    (input clk_i, input rst_i,
+     input we_i, input stb_i, input cyc_i, output reg ack_o,
+     input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+     output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
+   
    // Register Map
-   // 0  8 bits   Read -- buffer level, Write -- char to send
-   // 1  16 bits  Clock Divider 
-   // 2           Control Register
-
-   wire   wb_acc = cyc_i & stb_i;            // WISHBONE access
-   wire   wb_wr  = wb_acc & we_i;            // WISHBONE write access
-
-   wire   tx_fifo_full;
-   assign rx_int_o = 0;
+   localparam SUART_CLKDIV = 0;
+   localparam SUART_TXLEVEL = 1;
+   localparam SUART_RXLEVEL = 2;
+   localparam SUART_TXCHAR = 3;
+   localparam SUART_RXCHAR = 4;
    
+   wire       wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire       wb_wr  = wb_acc & we_i;            // WISHBONE write access
+   
    reg [15:0] clkdiv;
-   wire [7:0] tx_fifo_level;
-   wire [7:0] rx_fifo_level = 0;
-   reg [31:0] ctrl;
+   wire [7:0] rx_char;
+   wire       tx_fifo_full, rx_fifo_empty;   
+   wire [7:0] tx_fifo_level, rx_fifo_level;
+   
    always @(posedge clk_i)
      if (rst_i)
        ack_o <= 1'b0;
@@ -28,27 +30,32 @@
    
    always @(posedge clk_i)
      if (rst_i)
-       begin
-         clkdiv <= 0;
-         ctrl <= 0;
-       end
+       clkdiv <= 0;
      else if (wb_wr)
-       case( adr_i)
-        1 : clkdiv <= dat_i[15:0];
-       endcase // case( adr_i[3:2] )
+       case(adr_i)
+        SUART_CLKDIV : clkdiv <= dat_i[15:0];
+       endcase // case(adr_i)
    
    always @(posedge clk_i)
      case (adr_i)
-       0 : dat_o <= tx_fifo_level;
-       1 : dat_o <= ctrl;
+       SUART_TXLEVEL : dat_o <= tx_fifo_level;
+       SUART_RXLEVEL : dat_o <= rx_fifo_level;
+       SUART_RXCHAR : dat_o <= rx_char;
      endcase // case(adr_i)
-      
-   simple_uart_tx uart_tx
+   
+   simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx
      (.clk(clk_i),.rst(rst_i),
-      .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i == 0)),
+      .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i == 
SUART_TXCHAR)),
       .fifo_level(tx_fifo_level),.fifo_full(tx_fifo_full),
       .clkdiv(clkdiv),.baudclk(baud_o),.tx(tx_o));
-     
-   assign tx_int_o = ~tx_fifo_full;   
    
+   simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx
+     (.clk(clk_i),.rst(rst_i),
+      .fifo_out(rx_char),.fifo_read(ack_o && ~wb_wr && (adr_i == 
SUART_RXCHAR)),
+      .fifo_level(rx_fifo_level),.fifo_empty(rx_fifo_empty),
+      .clkdiv(clkdiv),.rx(rx_i));
+   
+   assign     tx_int_o = ~tx_fifo_full;
+   assign     rx_int_o = ~rx_fifo_empty;
+   
 endmodule // simple_uart

Added: usrp2/trunk/fpga/control_lib/simple_uart_rx.v
===================================================================
--- usrp2/trunk/fpga/control_lib/simple_uart_rx.v                               
(rev 0)
+++ usrp2/trunk/fpga/control_lib/simple_uart_rx.v       2008-06-26 05:09:23 UTC 
(rev 8719)
@@ -0,0 +1,19 @@
+
+
+module simple_uart_rx
+  #(parameter DEPTH=0)
+    (input clk, input rst, 
+     output [7:0] fifo_out, input fifo_read, output [7:0] fifo_level, output 
fifo_empty, 
+     input [15:0] clkdiv, input rx);
+
+   wire          write, full;
+   wire [7:0]    rcvd_char;
+   
+   medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo
+     (.clk(clk),.rst(rst),
+      .datain(rcvd_char),.write(write),.full(full),
+      .dataout(fifo_out),.read(fifo_read),.empty(fifo_empty),
+      .clear(0),.space(),.occupied(fifo_level[3:0]) );
+   assign        fifo_level[7:4] = 0;
+   
+endmodule // simple_uart_rx

Modified: usrp2/trunk/fpga/control_lib/simple_uart_tx.v
===================================================================
--- usrp2/trunk/fpga/control_lib/simple_uart_tx.v       2008-06-26 05:07:11 UTC 
(rev 8718)
+++ usrp2/trunk/fpga/control_lib/simple_uart_tx.v       2008-06-26 05:09:23 UTC 
(rev 8719)
@@ -1,21 +1,22 @@
 
 module simple_uart_tx
-  (input clk, input rst, 
-   input [7:0] fifo_in, input fifo_write, output [7:0] fifo_level, output 
fifo_full, 
-   input [15:0] clkdiv, output baudclk, output reg tx);
-
-   reg [15:0]  baud_ctr;
-   reg [3:0]   bit_ctr;
-
-   wire        read, empty;
-   wire [7:0]  char_to_send;
+  #(parameter DEPTH=0)
+    (input clk, input rst, 
+     input [7:0] fifo_in, input fifo_write, output [7:0] fifo_level, output 
fifo_full, 
+     input [15:0] clkdiv, output baudclk, output reg tx);
    
-   shortfifo #(.WIDTH(8)) fifo
+   reg [15:0]    baud_ctr;
+   reg [3:0]     bit_ctr;
+   
+   wire          read, empty;
+   wire [7:0]    char_to_send;
+   
+   medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo
      (.clk(clk),.rst(rst),
       .datain(fifo_in),.write(fifo_write),.full(fifo_full),
       .dataout(char_to_send),.read(read),.empty(empty),
-      .clear(0),.space(fifo_level[3:0]));
-   assign      fifo_level[7:4] = 0;
+      .clear(0),.space(fifo_level[3:0]),.occupied() );
+   assign        fifo_level[7:4] = 0;
    
    always @(posedge clk)
      if(rst)
@@ -54,7 +55,7 @@
         default : tx <= 1;
        endcase // case(bit_ctr)
 
-   assign      read = (bit_ctr == 9) && (baud_ctr == clkdiv);
-   assign      baudclk = (baud_ctr == 1);  // Only for debug purposes
+   assign        read = (bit_ctr == 9) && (baud_ctr == clkdiv);
+   assign        baudclk = (baud_ctr == 1);  // Only for debug purposes
    
 endmodule // simple_uart_tx