[Commit-gnuradio] r8477 - usrp2/trunk/fpga/sdr

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[Commit-gnuradio] r8477 - usrp2/trunk/fpga/sdr_lib

From:	matt
Subject:	[Commit-gnuradio] r8477 - usrp2/trunk/fpga/sdr_lib
Date:	Wed, 21 May 2008 16:47:17 -0600 (MDT)

Author: matt
Date: 2008-05-21 16:47:15 -0600 (Wed, 21 May 2008)
New Revision: 8477

Modified:
   usrp2/trunk/fpga/sdr_lib/HB.sav
   usrp2/trunk/fpga/sdr_lib/hb_dec.v
   usrp2/trunk/fpga/sdr_lib/hb_dec_tb.v
Log:
works all the way down to 2 samples per input strobe.  needs some thorough 
verification


Modified: usrp2/trunk/fpga/sdr_lib/HB.sav
===================================================================
--- usrp2/trunk/fpga/sdr_lib/HB.sav     2008-05-21 21:12:11 UTC (rev 8476)
+++ usrp2/trunk/fpga/sdr_lib/HB.sav     2008-05-21 22:47:15 UTC (rev 8477)
@@ -1,8 +1,7 @@
 [size] 1400 967
 [pos] -1 -1
-*-44.529663 5615000000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-46.395245 2565000000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] hb_dec_tb.
-[treeopen] hb_dec_tb.uut.
 @420
 hb_dec_tb.data_in[17:0]
 @28
@@ -13,12 +12,6 @@
 hb_dec_tb.uut.addr_even[3:0]
 @420
 hb_dec_tb.uut.data_even[17:0]
address@hidden
-hb_dec_tb.uut.addr_odd_a[3:0]
-hb_dec_tb.uut.addr_odd_b[3:0]
-hb_dec_tb.uut.addr_odd_c[3:0]
-hb_dec_tb.uut.addr_odd_d[3:0]
address@hidden
 hb_dec_tb.uut.data_odd_a[17:0]
 hb_dec_tb.uut.data_odd_b[17:0]
 hb_dec_tb.uut.data_odd_c[17:0]
@@ -28,9 +21,6 @@
 @420
 hb_dec_tb.uut.prod1[35:0]
 hb_dec_tb.uut.prod2[35:0]
-hb_dec_tb.uut.sum_of_prod[17:0]
-hb_dec_tb.uut.acc_out[19:0]
-hb_dec_tb.uut.acc_round[17:0]
 @24
 hb_dec_tb.uut.phase[2:0]
 @28
@@ -47,9 +37,20 @@
 hb_dec_tb.uut.coeff1[17:0]
 hb_dec_tb.uut.prod1[35:0]
 hb_dec_tb.uut.prod2[35:0]
-hb_dec_tb.uut.sum_of_prod[17:0]
-hb_dec_tb.uut.acc_out[19:0]
-hb_dec_tb.uut.acc_round[17:0]
 hb_dec_tb.uut.final_sum[17:0]
+hb_dec_tb.uut.coeff2[17:0]
+hb_dec_tb.uut.sum_of_prod[21:0]
 hb_dec_tb.data_out[17:0]
-hb_dec_tb.uut.coeff2[17:0]
address@hidden
+hb_dec_tb.uut.do_acc
+hb_dec_tb.uut.clear
address@hidden
+hb_dec_tb.uut.addr_odd_a[3:0]
+hb_dec_tb.uut.addr_odd_b[3:0]
+hb_dec_tb.uut.addr_odd_c[3:0]
+hb_dec_tb.uut.addr_odd_d[3:0]
address@hidden
+hb_dec_tb.uut.write_odd
+hb_dec_tb.uut.write_even
address@hidden
+hb_dec_tb.uut.data_even[17:0]

Modified: usrp2/trunk/fpga/sdr_lib/hb_dec.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_dec.v   2008-05-21 21:12:11 UTC (rev 8476)
+++ usrp2/trunk/fpga/sdr_lib/hb_dec.v   2008-05-21 22:47:15 UTC (rev 8477)
@@ -9,13 +9,14 @@
     (input clk,
      input rst,
      input bypass,
+     input [7:0] cpi,  // Clocks per input -- equal the decimation ratio ahead 
of this block
      input stb_in,
      input [IWIDTH-1:0] data_in,
      output reg stb_out,
      output reg [OWIDTH-1:0] data_out);
 
    // Control
-   reg [3:0]           addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d, 
addr_even;
+   reg [3:0]           addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d;
    wire                write_odd, write_even, do_mult;
    reg                         odd;
    reg [2:0]           phase, phase_d1;
@@ -52,9 +53,6 @@
      else
        stb_out_pre <= {stb_out_pre[14:0],(stb_in & odd)};
 
-   always @(posedge clk)
-     addr_even <= 7;
-   
    always @*
      case(phase)
        1 : begin addr_odd_a = 0; addr_odd_b = 15; end
@@ -78,7 +76,6 @@
    
    // Data
    wire [IWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d;
-   reg [IWIDTH-1:0]  data_even;
    wire [IWIDTH-1:0] sum1, sum2;       
    wire [OWIDTH-1:0] final_sum;
    reg [CWIDTH-1:0]  coeff1, coeff2;
@@ -114,16 +111,20 @@
    add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 
(.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1));
    add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 
(.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2));
 
-   wire [IWIDTH-1:0]   data_even_pre;
-   srl #(.WIDTH(IWIDTH)) srl_even
-     
(.clk(clk),.write(write_even),.in(data_in),.addr(addr_even),.out(data_even_pre));
+   wire [IWIDTH-1:0] data_even;
+   reg [3:0]        addr_even;
 
-   always @(posedge clk)
-     if(write_odd)
-       data_even <= data_even_pre;
+   always @*
+     case(cpi)
+       2 : addr_even = 9;
+       3, 4, 5, 6, 7 : addr_even = 8;
+       default : addr_even = 7;
+     endcase // case(cpi)
    
-   localparam          MWIDTH = ACCWIDTH-2;
-   
+   srl #(.WIDTH(IWIDTH)) srl_even
+     
(.clk(clk),.write(write_even),.in(data_in),.addr(addr_even),.out(data_even));
+
+   localparam          MWIDTH = ACCWIDTH-2;   
    wire [MWIDTH-1:0]   sum_of_prod;
 
    MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), 
.B(sum1) );
@@ -137,13 +138,6 @@
    acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) 
      acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out));
 
-   /*
-   round_reg #(.bits_in(ACCWIDTH),.bits_out(OWIDTH))
-     final_round (.clk(clk),.in(acc_out),.out(acc_round));
-
-   add2_and_round_reg #(.WIDTH(OWIDTH)) 
-     final_adder (.clk(clk), .in1(acc_round), .in2(data_even), 
.sum(final_sum));
-    */
    localparam          SHIFT_FACTOR = ACCWIDTH-IWIDTH-5;
    wire [ACCWIDTH-1:0]         data_even_signext, final_sum_unrounded;
 
@@ -153,14 +147,10 @@
    
    add2_and_round_reg #(.WIDTH(ACCWIDTH)) 
      final_adder (.clk(clk), .in1(acc_out), .in2(data_even_signext), 
.sum(final_sum_unrounded));
-   /*
-   round_reg #(.bits_in(ACCWIDTH),.bits_out(OWIDTH))
-     final_round (.clk(clk),.in(final_sum_unrounded),.out(final_sum));
-    */
+
    round_reg #(.bits_in(ACCWIDTH-5),.bits_out(OWIDTH))
      final_round 
(.clk(clk),.in(final_sum_unrounded[ACCWIDTH-6:0]),.out(final_sum));
 
-
    // Output
    always @(posedge clk)
      if(bypass)

Modified: usrp2/trunk/fpga/sdr_lib/hb_dec_tb.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_dec_tb.v        2008-05-21 21:12:11 UTC (rev 
8476)
+++ usrp2/trunk/fpga/sdr_lib/hb_dec_tb.v        2008-05-21 22:47:15 UTC (rev 
8477)
@@ -1,7 +1,7 @@
 module hb_dec_tb( ) ;
    
     // Parameters for instantiation
-    parameter               clocks  = 20 ; // Number of clocks per input
+    parameter               clocks  = 8'd2 ; // Number of clocks per input
     parameter               decim   = 1 ; // Sets the filter to decimate
     parameter               rate    = 2 ; // Sets the decimation rate
 
@@ -48,8 +48,8 @@
     */
 
    
-   hb_dec #(.IWIDTH(18),.OWIDTH(18),.CWIDTH(18),.ACCWIDTH(20)) uut
-     (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in),
+   hb_dec #(.IWIDTH(18),.OWIDTH(18),.CWIDTH(18),.ACCWIDTH(24)) uut
+     
(.clk(clock),.rst(reset),.bypass(0),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in),
       .stb_out(strobe_out),.data_out(data_out) );
    
     integer i, ri, ro, infile, outfile ;
@@ -113,7 +113,7 @@
         else
             $display( "PASSED: Simulation successful" ) ;
 
-        $stop ;
+        $finish ;
     end
 
    // Output comparison of simulated values versus known good values

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